Permutable Interconnects for FPGA Routing Bottlenecks
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Solution Overview
Problem
The existing placement and routing processes for integrated circuits, particularly in emulation systems using FPGAs, often result in over-constrained designs due to the lack of means to specify symmetrical equivalence of interconnect signals, leading to routing bottlenecks and long routing times.
Innovation Solution
The technique allows users to specify and permute symmetrically equivalent interconnect signals, enabling place-and-route tools to minimize routing bottlenecks by defining groups of permutable signals and optimizing connections between independently created blocks, such as IP blocks, without the need for explicit connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional placement and routing processes are used without specifying symmetrical equivalence of interconnect signals, then routing constraints are overly restrictive, but routing time increases and routing failures occur
Solution Approach 1:
The patent changes the constraint parameters by introducing symmetrical equivalence relationships between interconnect signals. Instead of treating each signal connection as a unique constrained entity, the system groups signals that are symmetically equivalent and allows them to be routed flexibly among equivalent paths, thereby reducing routing constraints while maintaining routing success.
Solution Approach 2:
The patent makes routing paths universal by allowing multiple equivalent signals to share the same routing resources. The symmetrical equivalence mechanism enables any signal within an equivalence group to use any available path designated for that group, creating a multi-functional routing system that reduces bottlenecks and improves both success rate and efficiency.
2Manufacturing precision
If explicit connections are specified for all interconnect signals, then routing constraints are precise, but device complexity and routing difficulty increase
Solution Approach 1:
The patent merges multiple explicit connection specifications into unified symmetrical equivalence groups. Instead of individually constraining each signal connection, the system combines signals with equivalent routing requirements into groups, where a single set of routing resources serves multiple signals. This reduces routing complexity while maintaining connection accuracy through the equivalence relationships.
Solution Approach 2:
The patent uses copying by creating equivalent routing paths for symmetrical signals. Rather than specifying unique paths for each signal, the system creates template paths that can be copied and assigned to multiple equivalent signals, reducing the complexity of connection specifications while ensuring accurate routing for all signals in the group.
3Productivity
If routing resources are tightly constrained without signal permutation, then routing paths are deterministic, but routing bottlenecks occur and routability decreases
Solution Approach 1:
The patent introduces dynamics by enabling permutation of interconnect signals within symmetrical equivalence groups. The routing system can dynamically assign different signals to different paths based on resource availability, rather than following fixed deterministic assignments. This dynamic allocation eliminates bottlenecks and improves both routing efficiency and overall routability.
Solution Approach 2:
The patent creates composite routing resources by combining multiple equivalent paths into unified routing groups. These composite resources can accommodate multiple signals through permutation, providing both the efficiency of resource sharing and the reliability of multiple available paths. The composite structure allows flexible signal assignment while maintaining deterministic routing within each equivalence group.
Data Source
AI summary
An improved placement and routing method for circuit simulation includes receiving setup input controls to set up an initial arrangement of two blocks (e.g., a synthesized block and an IP block), and a designation of permutable interconnections; performing permutations of permutable interconnect signals on the, e.g., design block (or any other block)-IP block arrangement to determine an optimal permutation; compiling a bitstream comprising a final placement and route of a circuit based on the optimal permutation and generating the bitstream to be loaded onto a target FPGA; and sending the final order of the permutable signals to a permutable signals control memory structure.