Permutation Apparatus Cache Segmentation for Memory Access Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional permutation techniques experience significant slowdowns due to random accesses to non-cache memory, which are much slower than cache memory accesses, especially when dealing with large datasets that exceed the cache capacity.
Innovation Solution
The technique involves segmenting data into smaller chunks that fit within the cache memory, performing sequential accesses to minimize cache misses, and switching to random accesses only when the cache hit ratio is high, thereby reducing the number of slow random accesses to non-cache memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional permutation techniques are used, then the permutation processing can be performed with simple implementation, but the processing speed becomes slow due to random accesses to non-cache memory
Solution Approach 1:
The patent divides the data into multiple segments that fit within the cache memory. By segmenting the data, the system can perform permutation operations on smaller data portions that remain in cache, avoiding frequent random accesses to non-cache memory. This segmentation strategy directly addresses the speed problem while maintaining manageable complexity through systematic data division.
Solution Approach 2:
The patent performs preliminary actions by pre-calculating permutation destinations and preparing data segments before the actual permutation operation. This preliminary preparation allows the main permutation process to execute more efficiently with fewer random memory accesses, thereby improving speed without significantly increasing operational complexity.
2Speed
If random accesses are performed on non-cache memory, then the permutation can be implemented with standard algorithms, but the access speed decreases by an order of magnitude
Solution Approach 1:
By segmenting the data into portions that fit within cache memory, the system eliminates random accesses to non-cache memory for the majority of data elements. This segmentation approach maintains high memory access speed by keeping data in fast cache memory while preserving permutation functionality, directly resolving the contradiction between access speed and processing throughput.
Solution Approach 2:
The patent introduces cache memory as an intermediary between the main memory and the permutation processing. By using cache memory as an intermediate storage layer, the system can perform permutation operations on data that fits in cache, avoiding direct random accesses to slower non-cache memory. This intermediary approach maintains high processing throughput while ensuring fast memory access speeds.
3Speed
If sequential accesses are used, then the memory access pattern becomes efficient, but the permutation algorithm becomes more complex
Solution Approach 1:
The patent segments the data and performs permutation operations on each segment sequentially, which improves memory access efficiency. By processing data in smaller sequential segments rather than large random accesses, the system achieves efficient memory access patterns. The segmentation approach manages algorithm complexity by breaking down the permutation problem into manageable sequential tasks.
Solution Approach 2:
The patent performs preliminary calculations to determine permutation destinations and prepare data segments before execution. This preliminary action enables the main processing to use efficient sequential access patterns, as the permutation targets are pre-determined. The preliminary preparation simplifies the main algorithm while achieving efficient sequential memory access, resolving the contradiction between access efficiency and algorithm complexity.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
To perform permutation processing at high speed. A number-of-elements determination unit (22) calculates the number of elements to be contained in each allocation destination. A start position determination unit (23) calculates a start position corresponding to each allocation destination. An allocation destination determination unit (24) calculates a sequence of values representing allocation destinations in a buffer. A permutation generating unit (25) calculates a sequence of values representing permutation destinations within the respective allocation destination. An initial position setting unit (31) sets the start position into a value indicating a position within processing corresponding to each allocation destination. A rearrangement unit (32) sets the elements of a vector into the respective allocation destinations in the buffer. A permutation execution unit (33) generates an output vector by executing an arbitrary inverse permutation algorithm on the respective allocation destinations.