Permutation Cipher Encryption for Processor-Accelerator MMIO

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Solution Overview

Problem

In cloud and high-volume data analytics computing environments, existing encryption methods like AES-GCM require large circuit area and power, leading to performance overhead and limiting widespread use for secure processor-accelerator communication, which is crucial for protecting against information leakage and spoofing attacks.

Innovation Solution

A lightweight cryptographic permutation technique is implemented, reducing circuit area and power consumption, enabling low-latency, high-throughput cryptographic operations directly on 64-bit data blocks without buffering or stalling data transfers, and providing security against information leakage, spoofing, and denial-of-service attacks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If AES-GCM encryption is used for processor-accelerator communication, then security is improved, but circuit area and power consumption increase

Engineering Contradiction:
ImprovesecurityVSAvoidcircuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the cryptographic approach from AES-GCM to a lightweight permutation-based cipher, fundamentally altering the encryption parameters to reduce circuit area while maintaining security. The permutation cipher uses simpler bitwise operations and smaller state requirements compared to AES-GCM, directly resolving the contradiction between security and circuit area.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs a lightweight cryptographic primitive that consumes fewer hardware resources, effectively using a simpler, more resource-efficient encryption mechanism. This disposable-like approach replaces the heavy AES-GCM implementation with a lighter permutation cipher that achieves security with minimal circuit area and power overhead.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Reliability

If AES-GCM encryption is used for processor-accelerator communication, then security is improved, but power consumption increases

Engineering Contradiction:
ImprovesecurityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent changes the cryptographic approach from AES-GCM to a lightweight permutation-based cipher, fundamentally altering the encryption parameters to reduce power consumption. The permutation cipher requires fewer computational operations and smaller hardware structures, directly reducing the energy consumed during encryption operations in processor-accelerator communication.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs a lightweight cryptographic primitive that consumes fewer hardware resources and less power. This simpler encryption mechanism replaces the power-intensive AES-GCM implementation, achieving security with minimal power overhead suitable for resource-constrained environments.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Reliability

If AES-GCM encryption is used for processor-accelerator communication, then security is improved, but latency increases

Engineering Contradiction:
ImprovesecurityVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the cryptographic approach from AES-GCM to a lightweight permutation-based cipher with fewer computational rounds and simpler operations. This parameter change reduces the time required for encryption/decryption operations, directly lowering latency in processor-accelerator communication while maintaining security through the permutation cipher's design.

Inventive Principle:
Principle #35Parameter changes

4Reliability

If AES-GCM encryption is used for processor-accelerator communication, then security is improved, but performance overhead increases

Engineering Contradiction:
ImprovesecurityVSAvoidperformance overhead
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the cryptographic approach from AES-GCM to a lightweight permutation-based cipher with simpler operations and smaller state requirements. This parameter change reduces the computational burden and resource utilization of encryption operations, minimizing performance overhead and allowing secure communication without significantly impacting overall system productivity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11838411B2Permutation cipher encryption for processor-accelerator memory mapped input/output communication
Publication Date: 2023.12.05 INTEL CORP
  • US11838411B2 patent drawing
  • US11838411B2 patent drawing
  • US11838411B2 patent drawing

AI summary

Technologies for secure data transfer of MMIO data between a processor and an accelerator. A MIMO security engine includes a first permutation cipher pipeline to defuse a count and a key into a permutation state; a first exclusive-OR (XOR) to generate ciphertext data from 64-bits of the new permutation state; and plaintext data; a concatenator to concatenate the plaintext data and additional authenticated data (AAD) to produce a concatenation result; a second XOR to generate an XOR result from the concatenation result and the latest permutation state; and a second permutation pipeline to generate an authentication tag of the XOR result and the key.