Permutation Respecting Hardware Verification Method
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Solution Overview
Problem
Current methods for verifying hardware designs that implement permutation respecting functions are inefficient and ineffective, particularly when using formal verification, as they take a long time to complete or fail to converge, especially for large input elements or complex functions.
Innovation Solution
The proposed method involves verifying that a hardware design is permutation respecting by checking that the output for any input vector and its permutation are permutation related, using a subset of input vectors and permutations, and reducing the verification space based on assumptions of permutation respecting properties for other permutations, thereby simplifying the verification process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification is used to verify hardware designs for permutation respecting functions, then verification completeness is improved, but verification time becomes excessively long or convergence fails
Solution Approach 1:
The verification process is segmented into two distinct phases: (1) verifying permutation respecting properties for a subset of input vectors, and (2) verifying correctness for remaining input vectors by applying permutations to the subset results. This segmentation divides the exhaustive verification task into manageable parts, achieving complete verification without requiring excessive time for all possible inputs.
Solution Approach 2:
The method performs preliminary verification on a subset of input vectors to establish permutation respecting properties before using these results to infer correctness for other input vectors. By performing this preliminary action on the subset, the verification process avoids repeating the same checks for all permutations, significantly reducing total verification time while maintaining completeness.
2Measurement precision
If exhaustive verification of all input vectors is performed, then verification accuracy is improved, but computational complexity increases significantly
Solution Approach 1:
The verification method uses universal permutation properties that apply across all input vectors. By verifying that the hardware design respects permutation properties for a subset of inputs, the same verification logic can be universally applied to infer correctness for all other inputs through permutation transformations, reducing computational complexity while maintaining verification accuracy.
Solution Approach 2:
Instead of independently verifying each input vector, the method creates copies of verification results from the subset by applying permutation transformations. These copied results serve as verification evidence for remaining input vectors, significantly reducing the computational burden of exhaustive verification while maintaining accuracy.
3Productivity
If the verification space is reduced by using subsets of input vectors, then verification efficiency is improved, but verification coverage may be compromised
Solution Approach 1:
The verification process uses feedback from the subset verification results to guide the verification of remaining input vectors. The permutation respecting properties established in the subset phase provide feedback that informs how to systematically verify other inputs, ensuring comprehensive coverage while maintaining efficiency. This feedback mechanism prevents loss of coverage by using subset results to drive complete verification.
Solution Approach 2:
The method transitions from verifying individual input vectors in one dimension to verifying permutation relationships across multiple dimensions. By moving to the dimension of permutation transformations, the approach achieves comprehensive verification coverage through subset results, as permutation properties inherently cover all possible input variations without requiring explicit verification of each case.
Data Source
AI summary
A hardware design for a component that implements a permutation respecting function is verified to be permutation respecting for a plurality of input vector permutations over all valid input vectors. For each input vector permutation in the plurality of input vector permutations, it is verified that the hardware design is permutation respecting for the input vector permutation by verifying that (i) an output of an instantiation of the hardware design in response to any input vector in a set of input vectors and (ii) an output of an instantiation of the hardware design in response to the input vector permutation of that input vector, are permutation related. The set of input vectors is selected based on an assumption that the hardware design is permutation respecting for at least one other input vector permutation of the plurality of input vector permutations.