Hardware Design Verification for Permutation Respecting Functions
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Solution Overview
Problem
Existing methods for formally verifying hardware designs for components that implement permutation respecting functions are inefficient and often unable to converge, especially when dealing with large input elements or complex functions, leading to prolonged verification times or inconclusive results.
Innovation Solution
The approach involves breaking down the verification process into smaller steps, where the hardware design is formally verified to produce correct outputs for a subset of valid input vectors and to be permutation respecting for specific input vector permutations, allowing any other input vectors to be generated through combinations of these permutations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification is performed on all valid input vectors, then verification completeness is improved, but verification time becomes excessively long and convergence is difficult
Solution Approach 1:
The patent segments the verification process into two distinct parts: (1) verifying correctness on a carefully selected subset of input vectors, and (2) verifying the permutation-respecting property for representative permutations. This segmentation allows the verifier to avoid exhaustively checking all possible input vectors while still guaranteeing complete verification coverage through mathematical reasoning about the permutation structure.
Solution Approach 2:
The patent performs preliminary action by first identifying and verifying the permutation-respecting property for a small set of representative permutations before concluding full verification. This preliminary verification of structural properties enables the system to infer correctness for all other permutations without explicit checking, significantly reducing verification time while maintaining completeness.
2Measurement precision
If formal verification is performed on complex functions with large input elements, then verification accuracy is maintained, but verification convergence becomes difficult or impossible
Solution Approach 1:
The patent extracts the permutation-respecting property as a separate, independently verifiable characteristic from the overall function correctness. By isolating this structural property, the verification system can handle complex functions with large input elements more efficiently, as verifying the permutation property is computationally simpler than verifying full functional correctness for all input combinations.
3Productivity
If a subset of input vectors and permutations is used for verification, then verification efficiency is improved, but verification coverage may be reduced
Solution Approach 1:
The patent makes the verification approach universal by selecting the subset of input vectors and permutations based on the specific characteristics of the permutation-respecting function being verified. This allows the same verification framework to efficiently handle different types of permutation-respecting functions (sorting, finding extrema, computing aggregates) while maintaining both efficiency and complete coverage through mathematically sound selection criteria.
Data Source
AI summary
Methods and systems for verifying a hardware design for a component that implements a permutation respecting function. The methods include formally verifying that an instantiation of the hardware design produces the correct result to the function for a subset of the valid input vectors; and formally verifying that an instantiation of the hardware design is permutation respecting for each of one or more input vector permutations (i.e. that the instantiation of the hardware design produces the permutation related outputs for an input vector and the permutation of that input vector) over a set of input vectors. The subset and the input vector permutations are selected so that any valid input vector that is not in the subset can be generated from an input vector in the subset via a combination of the one or more input vector permutations.