Permutation Shuffling Circuit Using Bit-Update Network Stages
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Solution Overview
Problem
Existing shuffling algorithms require excessive computational resources, time, and hardware area, making them inefficient for applications requiring random order changes.
Innovation Solution
A shuffling circuit and permutation shuffling device that utilizes a random code memory circuit, index register, and bit flip circuit to generate output index codes efficiently, minimizing computation and hardware area through a butterfly or Benes network scheme.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional shuffling algorithms (Fisher-Yates, Knuth) are used, then shuffling function is achieved, but computational resources, time, and hardware area become excessively large
Solution Approach 1:
The shuffling operation is divided into multiple independent bit update stages, where each stage updates specific bits of the index code based on random codes. This segmentation allows parallel processing and reduces the computational burden by breaking down the complex shuffling operation into manageable, independent stages.
Solution Approach 2:
The patent transforms the shuffling problem from a permutation-based approach to a bit-update approach. Instead of manipulating entire permutations, the system updates individual bits of index codes through multiple stages, effectively moving the problem to a lower dimensional space that requires fewer computational resources.
2Productivity
If traditional shuffling algorithms are implemented, then shuffling function is achieved, but hardware area becomes excessively large
Solution Approach 1:
Multiple shuffling stages are merged into a single integrated circuit structure that processes multiple bits simultaneously. The circuit combines random code storage, bit update logic, and index code generation into one unified hardware architecture, reducing the overall area required compared to separate implementations of traditional algorithms.
Solution Approach 2:
The circuit design is made universal by using the same basic building blocks (multiplexers, bit flip circuits) across all stages. The random code memory circuit and bit update logic can be reused for different shuffling operations, eliminating the need for dedicated hardware for each shuffling stage and significantly reducing total hardware area.
3Productivity
If traditional shuffling algorithms are used, then shuffling function is achieved, but computation time becomes excessively long
Solution Approach 1:
The shuffling operation proceeds through continuous bit update stages where each stage builds upon the previous one. The index code is updated bit by bit through multiple stages, with each stage contributing to the final shuffled result. This continuous process eliminates idle time and ensures that computation progresses without interruption, reducing total computation time.
Solution Approach 2:
Random codes are pre-generated and stored in the random code memory circuit before the shuffling operation begins. This preliminary preparation of random codes eliminates the need to generate randomness during the shuffling process, reducing the time required for computation and allowing the main shuffling operation to proceed more efficiently.
Data Source
AI summary
Some example embodiments provide a permutation shuffling device including a random code memory circuit configured to store first to nth random codes, and a first shuffling circuit configured to receive from outside a first input index code including first to nth input index bits, and to generate a first output index code by updating the first to nth input index bits based on the first to nth random codes, respectively.