Permuted Multi-Wire FEC for Burst-Error-Resilient Buses
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Solution Overview
Problem
High-speed chip-to-chip communication systems face challenges in reducing communication errors and latency due to burst errors and sequential data transmission methods, especially in multi-wire interfaces, which can be exacerbated by noise and skew across sub-channels.
Innovation Solution
The implementation of a permuter function that rearranges the order in which FEC-encoded data is transmitted across multiple sub-channels, distributing data streams to different sub-channel encoders in a cyclic or staggered manner to mitigate burst errors and reduce latency, using orthogonal sub-channel vectors and generalized Reed-Solomon codes for error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sequential data transmission is used across multiple sub-channels, then device complexity is reduced, but burst errors increase and reliability deteriorates
Solution Approach 1:
The patent divides the data transmission into multiple independent sub-channels (e.g., 4 sub-channels), each carrying a portion of the encoded data. This segmentation allows parallel transmission while maintaining simpler individual channel structures, resolving the contradiction between complexity and reliability.
Solution Approach 2:
The patent introduces a temporal dimension through permutation operations, rearranging data sequences across time slots and sub-channels. This transforms the transmission from simple sequential ordering to a multi-dimensional structure that disperses burst errors across different channels and times, improving reliability without significantly increasing complexity.
2Reliability
If permutation operations are applied to FEC-encoded data, then burst error protection improves, but device complexity increases
Solution Approach 1:
The permutation operation is performed in advance on the encoded data before transmission. This preliminary rearrangement ensures that burst errors affecting consecutive time slots will be dispersed across different logical data units, providing protection without requiring complex real-time processing during transmission.
Solution Approach 2:
The patent employs periodic permutation patterns that repeat at regular intervals, creating a predictable structure that simplifies both the permutation implementation and the corresponding de-permutation at the receiver. This periodicity reduces complexity while maintaining effective burst error protection.
3Productivity
If parallel sub-channel transmission is used, then data transmission speed increases, but skew and noise sensitivity increase causing more errors
Solution Approach 1:
By dividing data into multiple sub-channels for parallel transmission, the patent increases overall throughput while keeping individual channel requirements manageable. The segmentation allows speed improvement without proportionally increasing susceptibility to skew and noise on any single channel.
Solution Approach 2:
The permutation operation acts as an intermediary that decouples the relationship between physical transmission channels and logical data units. This intermediary layer allows the system to tolerate skew and noise by redistributing their effects across multiple logical units, enabling fast parallel transmission while mitigating harmful factors.
4Device complexity
If conventional FEC encoding is used without permutation, then device complexity is lower, but latency increases due to sequential error correction processing
Solution Approach 1:
The patent segments the error correction process into multiple parallel operations corresponding to different sub-channels. This allows simultaneous processing of multiple data units through the FEC decoder, reducing overall latency without requiring fundamentally more complex encoding structures.
Solution Approach 2:
By introducing permutation that operates across both spatial (sub-channel) and temporal (time slot) dimensions, the patent enables parallel decoding paths. This multi-dimensional approach allows latency reduction through parallel processing while maintaining relatively simple encoding structures.
Data Source
AI summary
Methods and systems are described for obtaining a plurality of information bits, and responsively partitioning the obtained plurality of information bits into a plurality of subsets of information bits, generating a plurality of streams of forward error correction (FEC)-encoded bits using a plurality of FEC encoders receiving respective subsets of the plurality of subsets of information bits, providing the plurality of streams of FEC-encoded bits to a plurality of sub-channel encoders, each sub-channel encoder receiving a respective stream of FEC-encoded bits from a different FEC encoder of the plurality of FEC encoders for generating a set of codewords of a vector signaling code, and wherein sequential streams of FEC-encoded bits from a given FEC encoder are provided to different sub-channel encoders for each successively generated set of codewords, and transmitting the successively generated sets of codewords of the vector signaling code over a multi-wire bus.