Permuted Multi-Wire FEC Transmission for Burst Error Robustness
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Solution Overview
Problem
In high-speed chip-to-chip communication systems, conventional methods face challenges in reducing communication errors and latency due to sequential transmission of FEC-encoded packets over multi-wire buses, which can lead to increased latency and vulnerability to burst errors.
Innovation Solution
The proposed solution involves permuting the transmission order of FEC-encoded packets across multiple sub-channels, using a permuter function to distribute FEC-encoded bits in a cyclically varying order, ensuring that sequential streams from one FEC encoder are transmitted on different sub-channels, thereby reducing latency and enhancing error correction robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FEC-encoded packets are transmitted sequentially over multi-wire buses, then the transmission process is simple, but latency increases and the system becomes vulnerable to burst errors
Solution Approach 1:
The patent divides the FEC-encoded bit stream into multiple parallel sub-channels, where each sub-channel carries a portion of the encoded data. This segmentation allows simultaneous transmission across multiple wires, reducing overall latency while maintaining error correction capabilities through distributed redundancy
Solution Approach 2:
The patent transitions from sequential single-channel transmission to parallel multi-channel transmission by adding a spatial dimension to the data flow. Multiple FEC-encoded packets are transmitted simultaneously across different sub-channels, converting a time-sequential process into a space-parallel process, thereby reducing latency without sacrificing reliability
2Reliability
If sequential streams from one FEC encoder are transmitted on the same sub-channel, then the encoding process is straightforward, but the system is vulnerable to burst errors
Solution Approach 1:
The patent applies a permuter function before transmission that pre-distributes sequential streams from the same FEC encoder across different sub-channels in a cyclically varying order. This preliminary arrangement ensures that burst errors affecting a single sub-channel do not corrupt entire FEC packets, as the error-prone bits are scattered across different codewords
Solution Approach 2:
The permuter function dynamically assigns different sub-channels to sequential streams based on a cyclic pattern that changes with each transmitted packet. This dynamic distribution adapts the mapping between data streams and physical channels, preventing systematic vulnerability to sub-channel-specific interference while maintaining manageable complexity through regular permutation patterns
3Productivity
If multiple FEC encoders process different subsets of information bits, then parallel processing is achieved, but coordination across encoders becomes complex
Solution Approach 1:
The patent divides the incoming information bit stream into multiple subsets, with each subset processed by a separate FEC encoder operating in parallel. This segmentation enables simultaneous error correction encoding across multiple data portions, increasing throughput while the subsequent permuter function coordinates the output streams through a systematic distribution pattern
Data Source
AI summary
Methods and systems are described for obtaining a plurality of information bits, and responsively partitioning the obtained plurality of information bits into a plurality of subsets of information bits, generating a plurality of streams of forward error correction (FEC)-encoded bits using a plurality of FEC encoders receiving respective subsets of the plurality of subsets of information bits, providing the plurality of streams of FEC-encoded bits to a plurality of sub-channel encoders, each sub-channel encoder receiving a respective stream of FEC-encoded bits from a different FEC encoder of the plurality of FEC encoders for generating a set of codewords of a vector signaling code, and wherein sequential streams of FEC-encoded bits from a given FEC encoder are provided to different sub-channel encoders for each successively generated set of codewords, and transmitting the successively generated sets of codewords of the vector signaling code over a multi-wire bus.