Permuted LDPC Decoder Architecture for Faster Convergence
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Solution Overview
Problem
Current communication systems face challenges in achieving low bit error rates at high data rates due to the latency constraints of traditional concatenated codes, making them unsuitable for high-speed applications like 10 Gbps Ethernet and wireless standards, where LDPC codes offer near-capacity error correction but require efficient decoding methods to approach Shannon's limit.
Innovation Solution
The implementation of a novel LDPC decoder architecture that employs permuted accelerated decoding, utilizing daisy chains and APP (a posteriori probability) and check edge message updating, which allows for faster convergence and higher coding gains with fewer iterations, and can be pipelined to increase throughput and reduce hardware footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional concatenated codes are used, then error correction capability is provided, but latency constraints prevent achievement of low bit error rates at high data rates
Solution Approach 1:
The patent transforms the LDPC decoding problem by changing the processing order parameter through permutation of the parity check matrix rows and columns. This reordering enables a systematic processing sequence that accelerates convergence while maintaining error correction capability, allowing high data rates to be achieved with low bit error rates.
2Reliability
If LDPC codes with more decoder iterations are used, then coding gain and error correction performance improve, but decoding latency and processing time increase
Solution Approach 1:
The patent applies preliminary permutation to the parity check matrix before decoding begins. This pre-processing step reorders the matrix elements to create an optimal processing sequence that accelerates convergence during decoding, thereby achieving high coding gain with fewer iterations and reduced latency.
Solution Approach 2:
The patent introduces dynamic processing through the permuted systematic approach, where the decoding process adapts its sequence based on the reordered matrix structure. This dynamic reordering enables faster convergence compared to static traditional decoding methods, reducing the number of iterations needed to achieve target reliability.
3Productivity
If high-throughput LDPC decoding is implemented, then data rate capability increases, but hardware complexity and resource requirements increase
Solution Approach 1:
The patent segments the LDPC decoding process into systematically ordered stages based on the permuted matrix structure. This segmentation allows the decoder to process different sections of the code in an optimized sequence, achieving high throughput through efficient resource utilization without proportionally increasing hardware complexity.
Solution Approach 2:
The permuted systematic decoding architecture provides a universal framework that can handle different LDPC code rates and lengths through the same fundamental processing structure. This multi-functionality allows the hardware to achieve high throughput across various applications without requiring separate specialized circuits for each code configuration.
Data Source
AI summary
Permuted accelerated LDPC (Low Density Parity Check) decoder. This decoding approach operates by processing, in parallel, selected rows for multiple individual LDPC matrix rows from various sub-matrix rows (e.g., first group of rows from a first sub-matrix row, second group of rows from a second sub-matrix row, etc.). A memory structure of daisy chains is employed for memory management of APP (a posteriori probability) values and also for check edge messages/intrinsic information (λ) values. A first group of daisy chains may be employed for memory management of the APP values, and a second group of daisy chains may be employed for memory management of the check edge messages. These daisy chains operate to effectuate the proper alignment of APP (or gamma(γ)) values and check edge message/intrinsic information (λ) values for their respective updating in successive decoding iterations.