Perpendicular Interconnect Trunks for Multi-Chip Processor Coherence
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Solution Overview
Problem
As the number of compute elements on a processor semiconductor die increases, the complexity and size of the interconnect bus also grow, leading to challenges in managing efficient communication and maintaining coherence among elements while minimizing the die size.
Innovation Solution
A multi-chip processor apparatus with a primary interconnect trunk for on-chip communication and a secondary interconnect trunk for off-chip communication, both oriented perpendicularly to each other, along with distributed off-chip I/O interfaces, to manage coherence and data communication efficiently across multiple compute elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of compute elements on a processor semiconductor die increases, then information handling system performance is improved, but the size of the semiconductor die increases
Solution Approach 1:
The processor is divided into multiple compute elements (first compute element, second compute element, etc.) that can be independently configured and connected. Each compute element can be selectively connected to the interconnect bus, allowing performance scaling without proportionally increasing die size for unused elements.
Solution Approach 2:
The patent implements selective connectivity where not all compute elements are connected to all parts of the interconnect bus. The first compute element is connected to a first portion of the bus and the second compute element to a second portion, optimizing the interconnect structure to match actual communication needs and reducing unnecessary wiring.
2Adaptability or versatility
If the number of connecting runners or wires in the interconnect bus increases, then communication capability among compute elements is improved, but the size of the semiconductor die increases
Solution Approach 1:
The interconnect bus is segmented into multiple portions (first portion, second portion) that can be independently connected to different compute elements. This segmentation reduces the total number of wiring runners needed compared to a fully connected bus structure.
Solution Approach 2:
The patent introduces a third dimension of organization by separating compute elements and interconnect portions into distinct groups that can be selectively activated. This dimensional organization allows the system to scale communication capability without linearly increasing wire count across the entire die.
Data Source
AI summary
A multi-chip processor apparatus includes multiple processor chips on a substrate. At least one of the multiple processor chips includes a die with a primary interconnect trunk that communicates information between multiple compute elements situated along the primary interconnect trunk. That multiple processor chip includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of that multiple processor chip. The secondary interconnect trunk intersects the primary interconnect trunk at an intersection at which a bus control element is located. The bus control element includes a primary trunk interface that couples to the primary interconnect trunk at the intersection to enable the bus control element to control on-chip communication among the compute elements via coherency signals on the primary interconnect trunk. The bus control element includes a secondary trunk interface coupled to the secondary interconnect trunk.