Perpendicular Memory Block Architecture for Low-Warpage 3D Storage
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and reliability, particularly in minimizing warpage which can lead to defects and reduced integration density.
Innovation Solution
The semiconductor device design includes a configuration with first and second conductive plate structures on the same vertical level, featuring memory blocks and separation structures arranged in perpendicular horizontal directions, along with vertically stacked word lines and bit lines, to minimize warpage and enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity increases, but device warpage and defects increase
Solution Approach 1:
The semiconductor device is divided into multiple independent structures (first structure with first memory blocks, second structure with second memory blocks) arranged on different conductive plate structures. Each structure can be independently controlled and managed, allowing defect isolation and maintaining overall device reliability while achieving high storage capacity through 3D arrangement.
Solution Approach 2:
The patent transitions from 2D memory cell arrangement to 3D arrangement by stacking multiple conductive plate structures vertically at different levels. Memory blocks are arranged in both horizontal and vertical dimensions, with first memory blocks extending in a first horizontal direction and second memory blocks extending in a second horizontal direction perpendicular to the first, maximizing space utilization while maintaining structural stability.
2Manufacturing precision
If integration density is increased through 3D memory cell arrangement, then data storage capacity increases, but warpage occurs leading to defects
Solution Approach 1:
Multiple conductive plate structures are arranged symmetrically at different vertical levels to balance internal stresses. The first conductive plate structure supports first memory blocks while the second conductive plate structure supports second memory blocks, creating a balanced configuration that counteracts warpage forces and maintains planarity despite high integration density.
Solution Approach 2:
Different regions of the device are designed with different structural characteristics. First memory blocks and second memory blocks are arranged in perpendicular directions with different conductive plate structures, allowing localized stress distribution and preventing uniform warpage across the entire device while maintaining high integration density.
Data Source
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AI summary
A semiconductor device includes a first conductive plate structure and a second conductive plate structure, arranged at a same vertical level on a semiconductor chip and horizontally spaced apart from each other on the semiconductor chip, a first structure on the first conductive plate structure and including first separation structures and first memory blocks, and a second structure on the second conductive plate structure and including second separation structures and second memory blocks. The first memory blocks are spaced apart from each other by the first separation structures, and extend in parallel to each other in a first horizontal direction. The second memory blocks are spaced apart from each other by the second separation structures, and extend in parallel to each other in a second horizontal direction. The first and second horizontal directions are parallel to an upper surface of the first conductive plate structure, and are perpendicular to each other.