Perpendicular Source and Bit Lines for MRAM Array Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing density of MRAM arrays is limited by the minimum pitch width of parallel traces in conventional memory systems, which hinders further advancements in semiconductor fabrication and increases costs while compromising reliability.
Innovation Solution
Implementing a perpendicular source and bit line architecture in MRAM arrays, where the global source line is held at zero voltage and the write bias voltage goes from high to low, allowing for a tighter pitch without reducing the pitch width below minimums, and enabling the use of advancing semiconductor techniques without reaching pitch width limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If parallel source lines and bit lines are used in conventional MRAM arrays, then the array can be fabricated with current processes, but the pitch width between traces must be maintained above a minimum value which limits further density increases
Solution Approach 1:
The patent changes the conventional parallel arrangement of source lines and bit lines to a perpendicular arrangement. Instead of having both sets of lines run parallel to each other in the same plane, the source lines are oriented perpendicular to the bit lines, effectively utilizing a different spatial dimension for routing. This dimensional change allows for tighter pitch between traces while maintaining manufacturability with current semiconductor fabrication processes, thereby increasing memory cell density without compromising manufacturing precision.
2Quantity of substance
If the pitch width between parallel traces is reduced to increase density, then more memory cells can be fabricated in a given die area, but the minimum pitch width is jeopardized which compromises array functionality and reliability
Solution Approach 1:
By transitioning from a parallel to a perpendicular arrangement of source and bit lines, the patent enables tighter pitch between traces without compromising the minimum manufacturable width. This dimensional reorientation allows memory cells to be packed more densely in a given die area while maintaining the reliability and functionality of the array, as the perpendicular geometry provides better separation and reduces interference between adjacent traces.
Solution Approach 2:
The patent introduces asymmetry in the routing geometry by orienting source lines perpendicular to bit lines rather than maintaining symmetric parallel arrangements. This asymmetric configuration optimizes space utilization and allows for tighter pitch in critical dimensions while preserving signal integrity and device functionality, thereby increasing density without sacrificing reliability.
3Productivity
If advancing semiconductor fabrication techniques are used to increase density, then more memory can be produced, but the minimum pitch width limits are reached which halts further density improvements
Solution Approach 1:
The perpendicular arrangement of source and bit lines enables the patent to overcome the minimum pitch width limits imposed by current semiconductor fabrication techniques. By routing lines perpendicular to each other rather than parallel, the design achieves tighter effective pitch and higher density without requiring advances in manufacturing precision, thus maintaining productivity and enabling continued scaling with existing fabrication capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution increases MRAM array density, enhances performance, and reduces costs while maintaining reliability by eliminating the need for dual parallel bit and source lines, allowing for a more efficient use of space and reducing stress on transistors.
Implementation Method 1
Based on whether the free layer is in a parallel or anti-parallel alignment relative to the reference layer, either a one or a zero can be stored in each MRAM cell. Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell change due to the orientation of the magnetic fields of the two layers.
Implementation Method 2
The electrical resistance is typically referred to as tunnel magnetoresistance (TMR) which is a magnetoresistive effect that occurs in a MTJ.
Implementation Method 3
If a spin-polarized current is passed to the magnetic region of a free layer in the MTJ device, the electrons will transfer a portion of their spin-angular momentum to the magnetization layer to produce a torque on the magnetization of the free layer. Thus, this spin transfer torque can switch the magnetization of the free layer
Data Source
AI summary
A memory device comprising an array of memory cells wherein each memory cell comprises a respective magnetic random access memory (MRAM) element, a respective gating transistor, and a common wordline coupled to gates of gating transistors of said array of memory cells. The memory device further comprises a common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to said plurality of bit lines within said array of memory cells, and a plurality of bit lines which are routed parallel to each other and connected to the drains of said gating transistors, wherein each bit line is associated with a respective memory cell of said array of memory cells.