3D Stacked MRAM Arrays via Perpendicular Spin Current Injection
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Solution Overview
Problem
Magnetic random access memory (MRAM) cell size and write speed are limited by the saturation current of selection transistors and the breakdown of the tunnel barrier layer, preventing efficient spin-polarized current delivery for magnetization switching.
Innovation Solution
The implementation of a magnetic memory device with a stack of planar memory arrays, each comprising magnetic tunnel junctions with a free and pinned ferromagnetic layer and a tunnel barrier, where the resistance is controlled by a bidirectional spin-polarized current and a bias magnetic field, reducing the required spin-polarized current for switching and enhancing write speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If selection transistors are used to supply spin-polarized write current to MR elements, then magnetization switching can be achieved, but cell size is limited by transistor saturation current
Solution Approach 1:
The patent transitions from planar 2D current flow to 3D vertical current flow by directing spin-polarized current perpendicular to the magnetic layer surface through the tunnel barrier. This dimensional change enables more efficient current delivery to the magnetic layers, reducing the required current magnitude and allowing for smaller cell sizes while maintaining fast write speeds.
Solution Approach 2:
The patent changes the current delivery parameter from in-plane to perpendicular direction relative to the magnetic layer surface. This parameter change optimizes the spin-polarized current injection efficiency, reducing the saturation current requirement and enabling both smaller cell sizes and faster write operations.
2Speed
If higher magnitude spin-polarized current is applied to increase write speed, then write speed improves, but tunnel barrier layer breakdown occurs
Solution Approach 1:
The patent changes the current direction parameter from in-plane to perpendicular to the magnetic layer surface. This parameter change improves current injection efficiency and reduces the magnitude of current required for switching, thereby achieving faster write speeds without causing tunnel barrier breakdown.
Solution Approach 2:
The patent replaces the conventional in-plane current injection mechanism with a perpendicular current injection mechanism through the tunnel barrier. This substitution improves the efficiency of spin-polarized current delivery, reducing the current magnitude needed for magnetization switching and avoiding tunnel barrier damage while maintaining high write speeds.
3Device complexity
If one selection transistor is used per MR element, then device complexity is reduced, but required spin-polarized current cannot be supplied due to saturation
Solution Approach 1:
The patent changes the current injection direction from in-plane to perpendicular to the magnetic layer surface. This parameter change improves the efficiency of a single transistor's ability to deliver spin-polarized current, eliminating the need for multiple transistors per MR element while still achieving the required current magnitude for fast switching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a significant reduction in MRAM cell size and an increase in write speed by minimizing the spin-polarized current needed for magnetization reversal, improving endurance and efficiency.
Implementation Method 1
a tunnel barrier layer 14 disposed between the pinned and free magnetic layers
Implementation Method 2
The direction of the magnetization in the free layer 16 can be controlled by a direction of a spin-polarized current IS running through the element J in a direction perpendicular to a film surface
Implementation Method 3
A resistance of the MR element depends on a mutual orientation of the magnetizations in the magnetic layers 12 and 16
Data Source
AI summary
One embodiment of a magnetic memory device comprises a substrate and a plurality of planar memory arrays stacked on the substrate, each memory array includes a plurality of parallel first conductive lines, each first conductive line includes a ferromagnetic cladding, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of magnetic tunnel junctions, each magnetic tunnel junction has a controllable electrical resistance, is disposed at an intersection region and electrically coupled to one of the first conductive lines at its first end and to one of the second conductive lines at its second end. The electrical resistance of the magnetic tunnel junction is controlled by a joint effect of a spin-polarized current running between the first and second ends and a bias magnetic field applied simultaneously to said each magnetic tunnel junction. Other embodiments are described and shown.