Perpendicular Stacked FETs for Capacitance Reduction
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Solution Overview
Problem
Stacked field-effect transistors (FETs) face high capacitance issues due to overlapping areas such as fins and source/drain regions, which hinder device performance and wirability.
Innovation Solution
The FETs are oriented at an angle of ±90 degrees with respect to each other, reducing overlap between gate, source/drain, and channel regions, and utilizing epitaxial growth and high-k dielectric layers to minimize p-n coupling capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FETs are stacked vertically with overlapping fins and source/drain regions, then device density is improved, but capacitance increases due to overlapping areas
Solution Approach 1:
The patent applies asymmetry by rotating the second FET structure 90 degrees relative to the first FET, creating a non-symmetric stacked configuration. This asymmetric orientation causes the fins and source/drain regions of the two FETs to be perpendicular to each other, minimizing overlapping areas and reducing parasitic capacitance while maintaining vertical stacking for high density.
Solution Approach 2:
The patent transitions from a two-dimensional planar overlap problem to a three-dimensional solution by utilizing vertical stacking with rotational orientation. By adding the rotational dimension to the vertical stack, the fins and source/drain regions are arranged in different spatial planes, reducing capacitive coupling while maintaining compact footprint.
2Length of moving object
If gate-all-around technology is used for stacking NFET and PFET, then smaller scale devices are achieved, but unwanted high capacitance occurs due to too many overlapping areas
Solution Approach 1:
The patent resolves the capacitance issue in gate-all-around stacked devices by introducing asymmetric 90-degree rotation between stacked FETs. This asymmetric orientation ensures that while gates surround the channel regions, the fins and source/drain regions of upper and lower FETs are perpendicular, minimizing overlapping areas and reducing parasitic capacitance.
Solution Approach 2:
The patent changes the orientational parameter of the stacked FETs from parallel alignment to perpendicular alignment (90-degree rotation). This parameter change fundamentally alters the spatial relationship between fins and source/drain regions, reducing capacitive overlap while maintaining the compact gate-all-around structure.
3Object-generated harmful factors
If FETs are oriented perpendicular to each other in stacked configuration, then capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the first FET structure completely, then using it as a template or reference for forming the second FET structure with 90-degree rotation. This sequential approach with pre-established reference structures simplifies the manufacturing process compared to attempting to form both structures simultaneously with complex alignment requirements.
Solution Approach 2:
The patent segments the device fabrication into distinct stages: forming the first FET structure, then forming the second FET structure with rotational orientation. This segmentation allows each structure to be optimized and formed independently, reducing the overall manufacturing complexity despite the asymmetric configuration.
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a first field-effect transistor (FET) on a substrate, the first FET comprising a first plurality of channel regions extending in a first direction, and stacking a second FET on the first FET, the second FET comprising a second plurality of channel regions extending in a second direction perpendicular to the first direction, wherein the first FET comprises a first gate region extending in the second direction across the first plurality of channel regions, and the second FET comprises a second gate region extending in the first direction across the second plurality of channel regions.