Perpetual Digital Perceptron Parallel Processing Energy Reduction
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Solution Overview
Problem
The Von Neumann computing architecture is inefficient in terms of energy consumption and processing time due to its reliance on sequential logic computations, which contrasts with the parallel processing and energy efficiency of biological neural networks.
Innovation Solution
A digital in-memory processor, known as the Perpetual Digital Perceptron (PDP), utilizing hardwired ROM memory arrays for content and response memories, allowing for parallel processing of digital signals within a single feed-forward step, similar to neural networks, thereby reducing silicon cost and eliminating the need for reconfiguration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Von Neumann computing architecture with sequential logic computations is used, then processing can be performed with pre-written instructions, but energy consumption and processing time increase due to frequent memory accessing and sequential execution
Solution Approach 1:
The patent merges the storage and processing functions by implementing a content-addressable memory where the memory array itself performs pattern matching and computation. The memory cells directly compare input data with stored patterns and generate output signals without requiring sequential fetching and processing, thus combining storage and computation into a single parallel operation that reduces both energy consumption and processing time.
Solution Approach 2:
The patent pre-loads pattern data into the content-addressable memory array during system initialization or setup phase. This preliminary action allows the memory to be pre-configured with reference patterns, so that during operation, only the input data needs to be provided for immediate parallel comparison, eliminating the need for sequential pattern fetching during computation.
2Ease of manufacture
If ROM memory arrays are used for content and response memories, then silicon cost is reduced due to simplicity of hardwired storage, but reconfiguration capability is lost
Solution Approach 1:
The patent employs dynamic content-addressable memory structures that can be reconfigured through control signals and data loading mechanisms. While the base memory array uses simple ROM-like cells for cost-effectiveness, the system incorporates dynamic elements such as programmable decoders, selectable word lines, and configurable match criteria that allow the same hardware to adapt to different pattern matching tasks without requiring physical reconfiguration or additional complex memory structures.
Data Source
AI summary
An in-memory digital processor, Perpetual Digital Perceptron (PDP), is disclosed. The digital in-memory processor of the invention processes the input digital information according to a database of the digital content data stored/hardwired in the Content Read Only Memory (CROM) array and outputs the correspondent digital response data stored/hardwired in the Response Read Only Memory (RROM) array. The PDP is the hardwired digital in-memory processor without re-configuration capability and similar to the instinct functions of biological hardwired brains without re-shaping their neuromorphic structures from training and learning.