Persistent Cache Memory Write Tier for NAND Endurance

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Solution Overview

Problem

Storage systems using NAND SSDs face degradation due to high write amplification, leading to reduced endurance and performance, as they are prone to wear from frequent write operations.

Innovation Solution

Implementing a persistent cache memory region as a write tier, which offloads high-write skewed address spaces from NAND SSDs to extend endurance and enhance performance by directing write operations to a persistent memory region using machine learning techniques to anticipate and manage write densities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If write operations are directed to NAND SSDs to maintain storage system performance, then storage performance is improved, but NAND SSD endurance deteriorates due to high write amplification and wear from frequent write operations

Engineering Contradiction:
Improvestorage performanceVSAvoidNAND SSD endurance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The storage system segments write operations into two paths: high-write skewed address spaces are directed to the persistent memory region (PMR) while other address spaces continue to use NAND SSDs. This segmentation resolves the contradiction by isolating the wear-causing operations from the NAND SSDs while maintaining overall storage performance through the PMR path.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The persistent memory region acts as an intermediary between the host system and NAND SSDs for high-write workload. The disk adapter intermediates by analyzing IO workloads, identifying write-intensive address spaces, and redirecting them to PMR. This intermediary approach protects NAND SSDs from excessive write operations while maintaining storage system performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a persistent memory region is introduced to offload write operations from NAND SSDs, then NAND SSD endurance is improved, but device complexity increases due to additional memory regions and traffic management policies

Engineering Contradiction:
ImproveNAND SSD enduranceVSAvoidstorage system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The persistent memory region serves multiple functions: it acts as a write tier for high-write address spaces, provides a backup tier for data protection, and enables endurance enhancement for NAND SSDs. This multi-functionality justifies the added complexity by delivering multiple benefits from a single additional component.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The disk adapter automatically analyzes IO workloads, identifies high-write address spaces, and redirects traffic to appropriate tiers without manual intervention. The system self-manages the complexity of traffic policies and tiered storage management, reducing the operational burden despite the increased device complexity.

Inventive Principle:
Principle #25Self-service

3Productivity

If machine learning techniques are used to identify and direct write operations to persistent memory, then write amplification is reduced and performance is improved, but processing overhead increases due to IO workload analysis

Engineering Contradiction:
Improvestorage performanceVSAvoidprocessing overhead
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The disk adapter performs preliminary analysis of IO workloads to identify high-write address spaces before directing traffic to persistent memory or NAND SSDs. By pre-identifying and categorizing address spaces based on write density patterns, the system avoids real-time decision overhead during actual write operations, thus reducing processing overhead while maintaining performance benefits.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11816354B2Persistent memory adaptation
Publication Date: 2023.11.14 EMC IP HLDG CO LLC
  • US11816354B2 patent drawing
  • US11816354B2 patent drawing
  • US11816354B2 patent drawing

AI summary

Embodiments of the present disclosure relate to establishing persistent cache memory as a write tier. An input/output (IO) workload of a storage array can be analyzed. One or more write data portions of the IO workload can be stored in a persistent memory region of one or more disks of the storage array.