Persistent Memory Address Table Stale Bit Management
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Solution Overview
Problem
In storage systems, the logical-to-physical address table can become outdated when a write command is in progress, leading to 'data in flight' issues, where the physical address pointed to by the table no longer holds the current data, causing inconsistencies and potential data loss during power cycles or updates.
Innovation Solution
Implementing a stale bit in the logical-to-physical address table to mark entries as outdated and using ReRAM for storing the table, allowing direct updates and eliminating the need for delta copies, thereby ensuring data consistency and reliability across power cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the logical-to-physical address table is stored in non-volatile memory and copied to volatile memory for faster access, then read speed is improved, but data consistency deteriorates when write commands are in progress
Solution Approach 1:
The patent applies preliminary action by setting a stale bit in the logical-to-physical address table entry before the write operation completes. This proactive marking ensures that any subsequent read operations will detect the stale state and handle it appropriately, preventing inconsistent data retrieval while the write is in progress. The stale bit is set in advance of potential read conflicts, resolving the contradiction between fast volatile memory access and data consistency.
2Reliability
If the logical-to-physical address table is updated in non-volatile memory after write operations, then data consistency is improved, but access speed deteriorates due to non-volatile memory latency
Solution Approach 1:
The patent uses copying by maintaining a copy of the logical-to-physical address table in volatile memory while the original resides in non-volatile memory. The volatile memory copy enables fast access and updates during write operations, while the non-volatile memory copy ensures persistence and consistency across power cycles. This dual-copy approach resolves the contradiction by allowing fast operations on the volatile copy while periodically synchronizing with the non-volatile copy.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of the stale bit that mediates between the volatile and non-volatile memory copies of the address table. The stale bit acts as a flag that indicates when the volatile copy may be outdated, allowing the system to quickly determine whether to serve data from volatile memory or fetch it from non-volatile memory, thus resolving the speed-consistency tradeoff without requiring constant synchronization.
3Productivity
If delta copies are used to update the logical-to-physical address table, then update efficiency is improved, but system complexity increases
Solution Approach 1:
The patent extracts the essential update information by using only the stale bit indicator rather than maintaining complex delta copies of the entire address table. This extraction approach captures the critical consistency information needed to resolve write-in-flight issues while discarding the unnecessary complexity of full delta tracking. The system achieves update efficiency through this simplified extraction mechanism, avoiding the overhead of managing detailed delta versions.
Data Source
AI summary
A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.