Persistent Memory Barrier for Data Consistency
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Solution Overview
Problem
Existing data storage systems using non-volatile memory face issues with data consistency and corruption due to power failures or system resets, as updates to persistent memory can occur before the original data is fully stored, leading to inconsistent data being retained.
Innovation Solution
Implementing a persistent memory barrier instruction and cache coherence states to ensure that data is consistently stored in persistent memory before being considered persistent, and using a queue with pointers to manage data access and synchronization between threads or processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is stored in persistent memory using multiple threads and processors simultaneously, then productivity and data access speed are improved, but data consistency and reliability deteriorate due to potential corruption from power failures or system resets
Solution Approach 1:
The patent applies preliminary action by implementing a persistent memory barrier instruction that forces all previous store instructions to be committed to persistent memory before the barrier completes. This ensures that data is safely persisted before subsequent operations proceed, preventing corruption from power failures while maintaining multi-threaded productivity.
Solution Approach 2:
The persistent memory barrier instruction acts as an intermediary mechanism between multiple threads and processors accessing persistent memory. It coordinates access by ensuring proper ordering and visibility of memory operations across different execution contexts, maintaining consistency without sacrificing parallel productivity.
2Device complexity
If store operations are allowed to complete in any order without synchronization, then device complexity is reduced, but data consistency deteriorates as updated variables may be persisted before original data
Solution Approach 1:
The persistent memory barrier instruction requires all previous store instructions to be completed and committed to persistent memory before the barrier instruction completes. This preliminary commitment ensures data consistency without requiring complex synchronization protocols, maintaining relatively simple device architecture.
3Speed
If data is buffered in volatile memory before persistent storage, then data transfer speed is improved, but data loss risk increases during power failures before data is flushed to persistent memory
Solution Approach 1:
The persistent memory barrier instruction ensures that data is committed to persistent memory before subsequent operations proceed. This preliminary commitment to persistent storage protects against data loss from power failures while maintaining the performance benefits of volatile memory buffering through proper synchronization.
Data Source
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AI summary
Systems and methods for reliably using data storage media. Multiple processors are configured to access a persistent memory. For a given data block corresponding to a write access request from a first processor to the persistent memory, a cache controller prevents any read access of a copy of the given data block in an associated cache. The cache controller prevents any read access while detecting an acknowledgment that the given data block is stored in the persistent memory is not yet received. Until the acknowledgment is received, the cache controller allows write access of the copy of the given data block in the associated cache only for a thread in the first processor that originally sent the write access request. The cache controller invalidates any copy of the given data block in any cache levels below the associated cache.