Persistent Memory Storage Engine Using Volatile Index and Batch Logging
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Solution Overview
Problem
Existing persistent memory storage engine designs face challenges in achieving both low latency and high throughput due to high CPU overhead from index maintenance and synchronization issues, particularly in multi-core platforms, where traditional log structures conflict in reducing latency and bandwidth.
Innovation Solution
A log-structured persistent memory key-value storage engine is designed with persistent memory allocators, compact log entries, and a volatile index structure, utilizing batch persistency and pipeline batch persistence technology to reduce CPU overhead and latency, while ensuring high system throughput by synchronizing processor cores and optimizing memory allocation and indexing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional index structures (hash-based or tree-based) are maintained in persistent memory, then data access efficiency is improved, but CPU overhead increases hugely due to rehashing, moving key-value entries, and cache line eviction operations
Solution Approach 1:
The patent extracts the index structure from persistent memory and places it in volatile memory (DRAM). The persistent memory stores only key-value data in a simplified log structure, while the volatile index structure in DRAM provides fast access paths. This separation eliminates the CPU overhead of maintaining index structures in persistent memory while preserving fast data access capabilities.
Solution Approach 2:
The patent introduces a volatile memory buffer as an intermediary between the persistent memory log structure and the processing cores. This buffer cache stores recently accessed key-value pairs and index information, mediating between the fast volatile memory and the persistent storage, thereby reducing CPU overhead for persistent memory operations while maintaining fast access performance.
2Productivity
If batch processing is used to provide high bandwidth, then throughput is improved, but latency increases due to the need to accumulate multiple requests
Solution Approach 1:
The patent performs preliminary actions by pre-allocating memory buffers and preparing batch processing structures in advance. Requests are queued in pre-allocated buffer spaces, and batch processing is triggered when buffers are full or at scheduled intervals, reducing the time needed to prepare for batch operations while maintaining high throughput.
Solution Approach 2:
The patent implements dynamic batch processing where the batch size and timing are adjusted based on system conditions. The batch processing mechanism can switch between immediate batching when buffers are full and more frequent smaller batches when latency is critical, dynamically optimizing the trade-off between throughput and latency based on current workload and system state.
3Reliability
If log structure is used for crash consistency and reducing persistent memory fragmentation, then data persistence is improved, but the opportunity to fully utilize batch processing to reduce persistence overhead is lost
Solution Approach 1:
The patent merges multiple individual persistence operations into a single batch persistence operation. By accumulating multiple log entries in a buffer and writing them together in one atomic persistent memory operation, the system maintains crash consistency (all or nothing) while dramatically reducing the total number of persistence operations and their associated overhead.
Solution Approach 2:
The patent performs preliminary actions by pre-formatting and buffering log entries before persistence. Log entries are prepared, validated, and organized in advance in volatile memory buffers, so that when persistence is triggered, the actual write operation is minimized to a single batch operation, reducing persistence overhead while ensuring crash consistency through atomic commit semantics.
4Speed
If RDMA high-speed network devices with user-mode polling are used to reduce latency, then access speed is improved, but overall bandwidth is affected due to large CPU time for polling
Solution Approach 1:
The patent extracts the polling function from user-mode application space and implements it in kernel-mode or as a separate background service. This allows the polling mechanism to operate with higher privileges and more efficient context switching, reducing the CPU time overhead while maintaining the low-latency benefits of RDMA for time-critical operations.
Solution Approach 2:
The patent implements dynamic polling strategies where the polling frequency and intensity are adjusted based on system conditions. During periods of high latency sensitivity, polling is intensified; during periods when throughput is more critical, polling frequency is reduced. This dynamic adjustment allows the system to optimize between access speed and overall bandwidth based on current workload characteristics.
Data Source
AI summary
The present invention provides persistent memory storage engine device based on log structure and a control method, including persistent memory allocators, persistent operation logs, and a volatile index structure. The control method of log structure-based storage engine includes: allocating by persistent memory allocators, new spaces to each processor for storing updated key value pairs; organizing acquired operation information into compact log entries, and adding compact log entries into persistent operation logs according to first preset rule, where first preset rule is performing batch persistency on compact log entries from the plurality of processor cores; and updating index entries in volatile index structure to point to new key value pairs. This application fully exploits opportunity to reduce persistence overhead by redesigning log structure storage format and batch persistence mode. An efficient persistent memory key-value storage engine based on log structure is designed which reduces latency while maintaining high system throughput.