Persistent Memory Cache Coherence Protocol States
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Solution Overview
Problem
Current cache coherence protocols, such as MESI, MOSI, and MOESI, are inadequate in managing cache coherency in systems that incorporate persistent memory, particularly phase change memory (PCM), as they do not effectively handle the non-volatile nature and asymmetric read/write speeds of PCM, leading to potential synchronization issues and inefficiencies in multi-processor systems.
Innovation Solution
The introduction of additional cache coherence states, such as 'in-process' and 'committed' states, along with a persistent memory descriptor, to manage cache coherency in systems with persistent memory, ensuring that processors synchronize local caches with main memory and handle updates efficiently, thereby preventing race conditions and maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cache coherence protocols (MESI, MOSI, MOESI) are used in systems with persistent memory, then existing coherency management mechanisms are maintained, but synchronization issues and inefficiencies occur due to inability to handle non-volatile nature and asymmetric read/write speeds of PCM
Solution Approach 1:
The patent extends the traditional MESI protocol by adding new state parameters (P-bit and C-bit) to track persistent memory update status. The protocol introduces five states (M, E, S, I, and a fifth state for in-process updates) to accurately represent the coherency status of cache lines when persistent memory is involved, enabling proper handling of asymmetric read/write speeds and non-volatile characteristics.
Solution Approach 2:
The patent implements dynamic state transitions that adapt to the persistent memory's unique characteristics. The memory controller dynamically manages the in-process state by setting P-bit when a write operation is pending and clearing it when complete. The protocol dynamically adjusts coherence management behavior based on whether a cache line is in the process of being updated, allowing efficient handling of the non-volatile nature of PCM.
2Reliability
If additional cache coherence states (in-process, committed) are introduced to manage persistent memory coherency, then data integrity and synchronization are improved, but protocol complexity increases
Solution Approach 1:
The patent makes the existing MESI protocol multi-functional by reusing the same state machine and transition logic to handle both traditional volatile memory and persistent memory scenarios. The additional P-bit and C-bit fields are integrated into the existing coherence management framework, allowing the same protocol mechanism to serve multiple purposes: managing coherence for regular memory accesses and for persistent memory updates, thereby reducing the need for entirely separate protocol paths.
Solution Approach 2:
The patent introduces an intermediary state (the fifth state for in-process updates) that acts as a mediator between the cache and persistent memory. This intermediate state, along with the P-bit and C-bit flags, serves as a communication mechanism between the memory controller and processors, coordinating the asynchronous update operations and ensuring proper synchronization without requiring complex protocol changes throughout the entire system.
3Reliability
If frequent data flushing or checkpointing is performed to maintain coherency with persistent memory, then data consistency is ensured, but system performance deteriorates
Solution Approach 1:
The patent performs preliminary actions by setting the P-bit flag when a write operation to persistent memory is initiated, before the actual write completes. This allows other processors to see the in-process state and delay their reads or invalidations until the update is complete (indicated by clearing the P-bit), eliminating the need for frequent flushing or checkpointing operations while maintaining consistency.
Solution Approach 2:
The patent implements feedback mechanisms through the P-bit and C-bit flags that continuously report the status of persistent memory updates to the memory controller and processors. This feedback loop allows the system to automatically adjust coherence management behavior based on the actual state of persistent memory updates, reducing unnecessary data flushing operations and improving performance while maintaining consistency.
Data Source
AI summary
A memory device having a memory controller, a main memory with at least a portion comprising persistent memory, and at least two processing entities, wherein the memory controller enables the processing entities to access the main memory according to a cache coherence protocol. The cache coherency protocol can signal when the main memory is being updated and when the update has finished. The processing entities can be configured to wait for the main memory to be updated or can access previously stored memory.