Persistent Memory Write Cache in NVMe Storage Array Enclosure
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Solution Overview
Problem
Conventional data storage approaches that replicate write data to persistent memory in multiple storage nodes increase cost and complexity, and lead to limited data replication and high-availability issues when one storage processor becomes unavailable.
Innovation Solution
Implementing a persistent memory write cache within the storage array enclosure, accessible via RDMA operations and NVMe-oF, allowing write data to be cached and replicated independently of storage processors, with dual controllers and persistent memory devices for high-availability and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write data is replicated to persistent memory in multiple storage nodes, then data redundancy and reliability are improved, but system cost and complexity increase
Solution Approach 1:
The patent extracts the persistent memory write cache from the storage processor and places it within the storage array enclosure. This separation removes the complexity of managing persistent memory at the storage processor level while maintaining data redundancy benefits. The storage array enclosure independently manages the persistent memory write cache, eliminating the need for complex inter-storage-processor communication for cache management.
Solution Approach 2:
The patent introduces NVMe-oF and RDMA as intermediary technologies enabling direct communication between storage processors and the persistent memory write cache in the storage array enclosure. This intermediary layer simplifies the system architecture by providing standardized protocols for data access without requiring complex custom integration between storage processors and persistent memory.
2Speed
If persistent memory is located in storage processors, then data access speed is improved, but high-availability is reduced when a storage processor becomes unavailable
Solution Approach 1:
The patent segments the storage system into independent components: storage processors for processing I/O requests and storage array enclosures for housing persistent memory write caches. This segmentation allows the persistent memory to remain accessible even when a specific storage processor is unavailable, as multiple storage processors can access the persistent memory in the storage array enclosure independently.
Solution Approach 2:
The patent changes the dimensional relationship between storage processors and persistent memory by moving persistent memory from being co-located within storage processors to being located in the storage array enclosure. This spatial reorganization allows multiple storage processors to access the same persistent memory resources, creating a multi-dimensional access topology that improves high-availability while maintaining fast access speeds through NVMe-oF and RDMA.
3Adaptability or versatility
If persistent memory write cache is implemented within storage array enclosure, then scalability is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the storage array enclosure to independently manage its persistent memory write cache without requiring complex coordination with storage processors. The storage array enclosure autonomously handles data writing to persistent memory using RDMA operations, eliminating the need for complex controller logic to manage cache coherence and data integrity across multiple controllers.
Data Source
AI summary
A method, computer program product, and computing system for receiving, via a storage processor of a storage system, a write request for writing a data portion to a storage array enclosure of non-volatile memory express (NVMe) drives communicatively coupled to the storage processor, where the write request may be received from a host. The data portion may be written to a persistent memory write cache within the storage array enclosure.