Persistent Memory Cache Management via Steal Write-Back

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Solution Overview

Problem

Current methods for maintaining data consistency in persistent memory systems require significant CPU cache hardware modifications and introduce overheads that affect performance, as they need to manage write-back orders and data replication efficiently.

Innovation Solution

A method and apparatus for cache management in persistent memory that uses a steal write-back technology for uncommitted data persistence and a no-force write-back technology for committed data, allowing bulk persistence and reducing the need for hardware support, by allocating space directly in non-volatile memory and utilizing persistent replicas for caching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If CPU cache hardware is modified to support state tracking and guarantee write-back order, then data consistency is improved, but device complexity increases

Engineering Contradiction:
Improvedata consistencyVSAvoidCPU cache hardware modification
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces hardware-based cache management mechanisms with a software-based transaction management system. Instead of modifying CPU cache hardware to track states and guarantee write-back order, the invention uses software transactions with metadata logs to manage data consistency, thereby avoiding hardware complexity while maintaining reliability

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces a transaction management layer as an intermediary between the CPU and persistent memory. This layer uses metadata logs and transaction protocols to mediate data consistency requirements, eliminating the need for direct hardware modifications to the CPU cache while ensuring reliable data consistency

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If flushing and fencing operations are introduced in persistent memory, then data consistency is improved, but productivity decreases

Engineering Contradiction:
Improvedata consistencyVSAvoidCPU cache efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the data consistency management functions from the CPU cache hardware and relocates them to the software transaction management layer. By removing the need for flushing and fencing operations from the hardware path, the invention eliminates performance overhead while maintaining consistency through software-based transaction protocols and metadata tracking

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If data is replicated frequently in persistent memory, then data consistency is improved, but loss of substance increases

Engineering Contradiction:
Improvedata consistencyVSAvoidmemory bandwidth
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The patent performs preliminary actions by maintaining metadata logs that track the state and location of data before actual data operations occur. This preliminary tracking allows the system to determine when data replication is actually necessary, avoiding unnecessary memory bandwidth consumption while ensuring data consistency through selective replication based on metadata state

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10379954B2Method and apparatus for cache management of transaction processing in persistent memory
Publication Date: 2019.08.13 TSINGHUA UNIVERSITY
  • US10379954B2 patent drawing
  • US10379954B2 patent drawing
  • US10379954B2 patent drawing

AI summary

The present invention provides a method and an apparatus for cache management of transaction processing in persistent memory. The method includes: when a transaction starts, reading old version data from non-volatile memory to a processor cache, and executing the transaction; during the execution of the transaction, allocating a space to generated new version data, and using a steal write-back technology to allow persistence of uncommitted data; when the transaction is committed or aborted, implementing forced persistence of transaction data to the non-volatile memory: after persistence of the transaction data or state is implemented to the non-volatile memory, writing the transaction data back to original data addresses, and using a no-force write-back technology to relax persistence of committed data to the non-volatile memory, where the transaction processing module periodically implements persistence of cached data to the non-volatile memory using bulk persistence; and when a system failure occurs, performing failure recovery processing on the transaction data. The method can reduce frequencies of data replication and data persistence in persistent memory.