Network-Attached Persistent Memory for Checkpoint Recovery

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Solution Overview

Problem

Existing systems face challenges in providing fast, granular access to persistent memory for checkpoint data, which is essential for efficient recovery from hardware or software failures, as they often rely on slow I/O storage devices or volatile system memory, leading to significant data loss and recomputation overhead.

Innovation Solution

A network-attached persistent memory unit (NPMU) that allows direct, low-latency access and storage of checkpoint data across multiple processor nodes, using RDMA-enabled networks to bypass kernel I/O processes and provide byte-level granularity, ensuring durability and recoverability similar to storage devices but with the speed of system memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If I/O storage devices are used to store checkpoint data, then data persistence is improved, but access speed deteriorates

Engineering Contradiction:
Improvedata persistenceVSAvoidaccess speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent introduces a network-attached persistent memory unit as an intermediary device between the processor and traditional I/O storage. This NPMU provides persistence similar to I/O storage but with memory-speed access through network interfaces, effectively mediating between the conflicting requirements of persistence and speed.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the access parameters by providing byte-level granularity access to persistent memory, unlike traditional block-oriented I/O storage. This parameter change enables fine-grained updates and faster access patterns while maintaining data persistence.

Inventive Principle:
Principle #35Parameter changes

2Speed

If system memory is used to store checkpoint data, then access speed is improved, but data persistence deteriorates

Engineering Contradiction:
Improveaccess speedVSAvoiddata persistence
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The network-attached persistent memory unit acts as a mediator that combines the speed characteristics of system memory with the persistence characteristics of I/O storage, allowing fast access without sacrificing data durability across power failures.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If BBDRAM is used for persistent memory, then access speed is improved compared to I/O storage, but global accessibility deteriorates

Engineering Contradiction:
Improveaccess speedVSAvoidglobal accessibility
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The network-attached persistent memory unit provides multi-functionality by serving as a shared resource accessible by multiple processors through the network, unlike BBDRAM which is typically confined to a single processor's fault domain. This enables universal access while maintaining fast performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Reliability

If block-oriented storage model is used, then data persistence is improved, but access granularity deteriorates

Engineering Contradiction:
Improvedata persistenceVSAvoidaccess granularity
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent fundamentally changes the access parameter from block-oriented to byte-level granularity. This allows individual bytes or small groups of bytes to be updated in persistent memory, enabling fine-grained checkpoint updates without requiring entire blocks to be rewritten, thus improving both efficiency and persistence.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9213609B2Persistent memory device for backup process checkpoint states
Publication Date: 2015.12.15 HEWLETT PACKARD ENTERPRISE DEV LP
  • US9213609B2 patent drawing
  • US9213609B2 patent drawing
  • US9213609B2 patent drawing

AI summary

A system is described that includes a network interface attached to a persistent memory unit. The persistent memory unit is configured to receive checkpoint data from a primary process, and to provide access to the checkpoint data for use in a backup process, which provides recovery capability in the event of a failure of the primary process. The network interface is configured to provide address translation information between virtual and physical addresses in the persistent memory unit. In other embodiments, the persistent memory unit is capable of storing multiple updates to the checkpoint state. The checkpoint state and the updates to the checkpoint state, if any, can be retrieved by the backup process periodically, or all at once upon failure of the primary process.