Secure Persistent Memory Counter Recovery Using Encrypted ECC
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Solution Overview
Problem
Emerging non-volatile memory (NVM) technologies face challenges in persisting encryption counters, leading to security vulnerabilities and performance degradation due to the need for frequent writes and reliance on backup power sources, which are costly and impractical in many scenarios.
Innovation Solution
The ECSC (Osiris) scheme repurposes Error-Correction Code (ECC) bits to verify the correctness of encryption counters, allowing for secure and fast recovery of lost counters without the need for external power sources or software modifications, reducing write traffic and performance overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encryption counters are persisted frequently to ensure security, then security reliability is improved, but write traffic increases and NVM lifetime decreases
Solution Approach 1:
The patent changes the parameter of counter persistence frequency by introducing a lazy update mechanism. Instead of persisting counters after every modification, the system accumulates counter changes in a cache and persists them periodically or triggered by specific events (e.g., cache full, power loss detection). This parameter change reduces write traffic from O(n) to O(1) or O(log n), thereby extending NVM lifetime while maintaining security through periodic synchronization.
Solution Approach 2:
The patent implements preliminary action by pre-allocation of counter cache space and pre-computation of counter values before actual persistence is needed. The system prepares counter updates in memory and only writes to NVM when necessary, rather than writing immediately after each counter change. This preliminary preparation in volatile memory reduces the frequency of NVM writes while ensuring counters are ready for immediate use.
2Reliability
If backup power sources are used to maintain encryption counters, then security reliability is improved, but system cost and complexity increase
Solution Approach 1:
The patent applies self-service by designing a counter cache management system that automatically detects power loss conditions and triggers appropriate recovery actions without external intervention. The system monitors cache state, detects power failures through hardware signals or software timeouts, and initiates counter persistence or recovery procedures autonomously. This eliminates the need for complex backup power management while maintaining counter integrity through self-managed fallback mechanisms.
Solution Approach 2:
The patent introduces an intermediary counter cache layer between the encryption logic and NVM storage. This cache acts as a buffer that decouples the frequent counter modifications from persistent storage requirements. The intermediary cache absorbs write amplification and allows the system to maintain counters in volatile memory during normal operation, only synchronizing to NVM when necessary, thereby reducing both complexity and write traffic.
3Duration of action of stationary object
If counter-cache schemes are used to reduce write traffic, then NVM lifetime is extended, but security vulnerabilities arise from lost counters
Solution Approach 1:
The patent implements feedback mechanisms where the system continuously monitors the state of the counter cache and compares it against expected values. After power recovery or suspected data loss, the system verifies counter integrity by checking checksums, version numbers, or cryptographic hashes stored alongside counter values. If verification fails, the system triggers recovery procedures such as re-computing counters from cryptographic primitives or restoring from checkpointed states, thereby maintaining reliability while using cache to extend NVM lifetime.
Solution Approach 2:
The patent applies beforehand cushioning by pre-computing and storing redundant counter information in the cache, such as backup counter values, cryptographic checkpoints, or verification data. This cushioning prepares the system in advance to handle potential counter loss scenarios without requiring complex recovery operations. The pre-stored redundancy acts as a safety buffer that allows the system to recover quickly and reliably from power losses or cache corruptions.
Data Source
AI summary
Disclosed herein are embodiment that are directed to a method comprising storing each encrypted data block, of a cyphertext page, with corresponding encrypted error correction code (ECC) bits in a persistent memory device (PMD). In exemplified embodiments, the encrypted ECC bits verify both an encryption counter value of an encryption operation and a plaintext block of the cyphertext page from a decryption operation. In other embodiments, the method includes decrypting, using the decryption operation during a read operation of a memory controller, a respective one block of the cyphertext file and the corresponding encrypted ECC bits stored in the PMD using a current counter value to form the plaintext block and decrypted ECC bits. Further, the may include verifying the plaintext block with the decrypted ECC bits; and performing a security check of the encryption counter value in response to the plaintext block failing the verification, using the decrypted ECC bits. A system and secure processor that are configured to perform the disclosed methods are provided.