Persistent Memory Flush Controller via Bus
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Solution Overview
Problem
Persistent memory devices often rely on volatile buffers, leading to uncertainties about data persistence, as data may not be immediately flushed to persistent memory, especially when accessed via buses like PCIe, resulting in lack of assurance that written data have been committed.
Innovation Solution
The implementation of a memory device with a volatile buffer and a memory controller that receives a flush instruction to immediately transfer data from the buffer to the target persistent memory, with optional range identification and flush attributes, allowing for efficient and assured data persistence without interrupting the central processing unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is written to persistent memory via a bus using volatile buffer, then write speed is improved, but data persistence reliability deteriorates
Solution Approach 1:
The system performs preliminary flushing of data from volatile buffer to persistent memory by issuing a flush instruction before the buffer is overwritten or lost. This preliminary action ensures data is safely persisted before any potential data loss event occurs, resolving the contradiction between fast buffering and reliable persistence.
Solution Approach 2:
The system implements feedback through completion messages that confirm when data has been successfully flushed to persistent memory. The flush instruction triggers a flush operation, and upon completion, a completion message is sent back to the sender, providing feedback that allows the system to verify data persistence reliability while maintaining high write speeds.
2Reliability
If immediate flushing is performed for all data, then data persistence reliability is improved, but system productivity deteriorates
Solution Approach 1:
The system applies local quality by allowing different memory regions to have different flush attributes. Some regions can be configured for immediate flushing (high reliability) while others use deferred or batched flushing (high productivity). This selective approach resolves the contradiction by optimizing each region according to its specific requirements rather than applying a uniform strategy system-wide.
Solution Approach 2:
The system performs partial flushing by selectively flushing only the necessary portions of data based on flush attributes and completion requirements. Instead of flushing all data immediately, it flushes only when required by flush instructions or completion messages, thereby maintaining productivity while ensuring reliability for critical data operations.
3Reliability
If CPU interrupts are generated for each write operation, then data persistence control is improved, but device complexity deteriorates
Solution Approach 1:
The system implements self-service by enabling the memory device to autonomously handle flush operations and generate completion messages without requiring continuous CPU intervention. The device can process flush instructions and manage data persistence independently, reducing the complexity of CPU-device interaction while maintaining reliable data persistence control through automated completion messaging.
Data Source
AI summary
A memory device includes a target memory, having a memory address space, and a volatile buffer memory, which is coupled to receive data written over a bus to the memory device for storage in specified addresses within the memory address space. A memory controller is configured to receive, via the bus, a flush instruction and, in response to the flush instruction, to immediately flush the data held in the buffer memory with specified addresses within the memory address space to the target memory.