Persistent Memory Data Mirroring via RDMA Offload

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Solution Overview

Problem

Current methods for protecting data against uncorrectable errors in Persistent Memory systems rely heavily on CPU resources, leading to increased workload and inefficiency, as data mirroring using CPU results in significant overhead.

Innovation Solution

Implementing asynchronous Persistent Memory access interfaces using RDMA Loopback or Intel DSA technology to perform data mirroring, offloading CPU-intensive operations to specialized hardware like RDMA devices, thereby reducing CPU utilization and maintaining data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If CPU-based data mirroring is used to protect data against uncorrectable errors, then data protection is achieved, but CPU workload increases significantly

Engineering Contradiction:
Improvedata protectionVSAvoidCPU workload
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces a dedicated data mirroring device as an intermediary component between the CPU and Persistent Memory. This device autonomously performs data mirroring operations, acting as a mediator that relieves the CPU of the mirroring burden while ensuring data protection. The intermediary device handles the repetitive mirroring tasks independently, allowing the CPU to focus on computational workloads.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The data mirroring device implements self-service by autonomously managing its own operations without requiring continuous CPU intervention. It independently performs mirroring, monitors status, and handles errors, thereby reducing CPU workload while maintaining reliable data protection. The system serves itself through automated mechanisms that eliminate the need for CPU-intensive manual management.

Inventive Principle:
Principle #25Self-service

2Reliability

If traditional CPU-based mirroring is implemented, then data integrity is maintained, but system performance and latency deteriorate

Engineering Contradiction:
Improvedata integrityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The dedicated data mirroring device serves as an intermediary that handles data integrity operations independently from the CPU. This separation allows parallel processing where the mirroring device maintains data integrity through specialized hardware operations, while the CPU continues execution without waiting for mirroring completion, thereby improving system performance and reducing latency.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the mechanical CPU-based mirroring process with a specialized data mirroring device that uses dedicated hardware circuits and memory controllers. This substitution eliminates the bottleneck of CPU instruction execution and data bus contention, enabling faster mirroring operations that maintain data integrity without sacrificing system performance.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12112054B2Coordinated persistent memory data mirroring
Publication Date: 2024.10.08 DELL PROD LP
  • US12112054B2 patent drawing
  • US12112054B2 patent drawing
  • US12112054B2 patent drawing

AI summary

Disclosed is a method for preforming the data mirror comprising: receiving from an application executing on a computing device a request to write data to a first local persistence memory of the computing device; issuing an async write operation to mirror the write request to write a same data to a second local persistence memory of the computing device by using a supplemental device; performing a write operation to write the data to the first local persistence memory by using a central processing unit (CPU) from the processing resource of the computing device; in response to determining that the write operation is completed and the async write operation is completed, determining a status check result indicating if the async write operation is successful; and sending the status check result to the application.