Persistent Memory Storage for Independent Node Caches

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Solution Overview

Problem

Modern storage clusters face inefficiencies due to the inability of nodes in volatile RAM to manage independent caches, requiring memory duplication and extra memory copies, and lack of cache policy control, leading to inefficiencies in data management during system failures.

Innovation Solution

Implement a vaulted memory management process using a primary and secondary node within a RAM with independent persistent areas, writing data to persistent media using an iterator, and managing dirty pages without the need for non-volatile random access memory (NVRAM) with a data journal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If volatile RAM with data journaling is used to optimize write operation latency, then write speed is improved, but the system cannot manage independent caches and requires memory duplication

Engineering Contradiction:
Improvewrite operation latencyVSAvoidmemory duplication and cache management
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent divides the RAM into multiple independent persistent areas, with each area assigned to a specific node. This segmentation allows each node to independently manage its own cache without requiring memory duplication across nodes, while maintaining fast write operations through the persistent nature of RAM.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each node is granted autonomous control over its designated persistent area, enabling it to independently manage its cache policies and data without external intervention. This self-service capability eliminates the need for complex centralized cache management and memory duplication mechanisms.

Inventive Principle:
Principle #25Self-service

2Reliability

If NVRAM is used to ensure data persistence during system failures, then data safety is improved, but device complexity and cost increase

Engineering Contradiction:
Improvedata persistence during failureVSAvoidNVRAM implementation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the fundamental parameter of memory volatility by utilizing persistent RAM that maintains data without power. This parameter change allows the system to achieve NVRAM-level reliability using RAM technology, avoiding the complexity and cost of actual NVRAM implementations while ensuring data persistence during system failures.

Inventive Principle:
Principle #35Parameter changes

3Speed

If traditional RAM cache is used without persistent areas, then memory access speed is improved, but data loss occurs during power disruption

Engineering Contradiction:
Improvememory access speedVSAvoiddata persistence during power failure
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system preliminarily designates specific persistent areas within the RAM structure before data writing operations. By pre-configuring these protected zones, the system ensures that critical data can be rapidly written to persistent locations during normal operation, maintaining high access speeds while preventing data loss during power disruptions.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12411616B2Storage system and method using persistent memory
Publication Date: 2025.09.09 EMC IP HLDG CO LLC
  • US12411616B2 patent drawing
  • US12411616B2 patent drawing
  • US12411616B2 patent drawing

AI summary

A method, computer program product, and computing system for sensing a failure within a system within a computing device. The system may include a cache memory system and a vaulted memory comprising a random access memory (RAM) having a plurality of independent persistent areas. A primary node and secondary node may be provided. The primary node may occupy a first independent persistent area of the RAM of the vaulted memory. The secondary node may occupy a second independent persistent area of the RAM of the vaulted memory. Data within the vaulted memory may be written to a persistent media using an iterator. The data may include at least one dirty page. Writing data within the vaulted memory to the persistent media may include flushing the at least one dirty page to the persistent media.