Persistent Memory Offloading via Acceleration Framework
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Solution Overview
Problem
The increasing use of persistent memory (PMEM) in data centers leads to a CPU resource burden, as each virtual machine's I/O operation on PMEM requires CPU blocking without interruption, challenging the guarantee of Quality of Service (QoS) for multiple virtual machines.
Innovation Solution
A lightweight acceleration framework is introduced to leverage offloading devices like Intel's Data Streaming Accelerator (DSA) or I/O Acceleration Technology (IOAT) to offload operations between DRAM and PMEM, reducing CPU utilization and enabling asynchronous API usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CPU is used to serve I/O operations on persistent memory for each virtual machine, then data access operations can be completed, but CPU resources become blocked and cannot serve other virtual machines, reducing overall system productivity
Solution Approach 1:
The patent extracts the I/O operation burden from the CPU by introducing an offloading device. The CPU transfers I/O requests to the offloading device, which then handles the persistent memory operations independently. This extraction allows the CPU to remain productive while I/O operations complete reliably.
Solution Approach 2:
The offloading device acts as an intermediary between the CPU and persistent memory. It receives I/O requests from the CPU, manages the complex operations with persistent memory, and returns results to the CPU. This mediator handles the blocking operations without preventing the CPU from serving other virtual machines.
2Reliability
If synchronous I/O operations are used with persistent memory, then data integrity can be ensured, but the CPU must wait for each operation to complete, increasing loss of time for serving multiple virtual machines
Solution Approach 1:
The offloading device performs I/O operations in advance or in parallel with CPU processing. By preparing and executing I/O operations independently before the CPU needs the results, the system ensures data integrity while eliminating CPU waiting time. The offloading device can initiate operations and continue processing without blocking.
Solution Approach 2:
The patent enables continuous CPU operation by decoupling I/O execution from CPU processing flow. The offloading device maintains continuous I/O operations independently, while the CPU continuously serves other virtual machines. Both operations proceed without interruption, eliminating wasted CPU time while maintaining data integrity through the offloading device's managed operations.
3Productivity
If multiple virtual machines share CPU resources for persistent memory access, then resource utilization improves, but QoS (Quality of Service) cannot be guaranteed for each VM due to CPU blocking
Solution Approach 1:
The patent segments the I/O processing function into separate components: the CPU handles virtual machine scheduling and high-level I/O request distribution, while the offloading device handles actual persistent memory operations. This segmentation allows each component to focus on its specialized function, enabling CPU to share resources among multiple VMs while the offloading device ensures reliable QoS for each VM's I/O operations independently.
Solution Approach 2:
The offloading device serves as an intermediary that guarantees QoS for each virtual machine's I/O operations. It receives requests from multiple VMs via the CPU, manages their execution with guaranteed service levels, and returns results. This mediator ensures that even while CPU resources are shared, each VM receives the QoS it requires for persistent memory access.
Data Source
AI summary
Examples relate to an apparatus, a device, a method, and a computer program for a computer system, and to a corresponding computer system. The apparatus comprises circuitry config-ured to provide an interface for accessing persistent memory provided by persistent memory circuitry of the computer system from one or more software applications. The circuitry is configured to translate instructions for performing operations on the persistent memory into corresponding instructions for offloading circuitry of the computer system, the corresponding instructions being suitable for instructing the offloading circuitry to perform the operations on the persistent memory. The circuitry is configured to provide the access to the persistent memory via the offloading circuitry.