Persistent Memory Flush Handling During Asynchronous Resets
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Solution Overview
Problem
Existing server designs fail to efficiently maintain persistent memory state during power loss events due to the limitations of battery backup units (BBUs) and asynchronous hardware resets, resulting in data loss or corruption, particularly in systems with persistent cache flushing, which is not handled by existing technologies.
Innovation Solution
The implementation of a system utilizing system power supply units (PSUs) to provide auxiliary energy for flushing volatile system memory to persistent memory after the loss of alternating current (AC) power, extending the hold-up window based on system power consumption, and managing multiple power supplies to ensure a full flush of processor caches and memory controller buffers without requiring a BBU.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If battery backup units (BBUs) are used to provide auxiliary energy for persistent cache flushing, then the system can maintain persistent memory state during power loss events, but the system suffers from large footprint, limited current supply capability, thermal constraints, and additional costs
Solution Approach 1:
The patent extracts the auxiliary energy storage function from the traditional BBU and relocates it to the PSU bulk capacitors. This removes the need for separate BBU components while maintaining the energy storage capability required for persistent cache flushing operations during power loss events
Solution Approach 2:
The PSU bulk capacitors, originally designed for general power supply functions, are made to serve dual purposes: maintaining power during normal operation and providing auxiliary energy for persistent cache flushing during power loss events. This eliminates the need for dedicated BBU components
2Reliability
If the hold-up window is extended to complete full cache flush operations, then persistent memory state is maintained, but the energy consumption increases
Solution Approach 1:
The system dynamically adjusts the hold-up window duration and power distribution based on real-time conditions. The power management logic monitors the energy available in PSU bulk capacitors and dynamically determines the appropriate hold-up period to complete cache flush operations without unnecessarily extending it, thereby optimizing energy consumption
Solution Approach 2:
The patent changes the parameter of energy distribution by redirecting power from non-essential system components to the cache flush operation during the hold-up window. This dynamic power reallocation ensures sufficient energy is available for persistent memory state maintenance while minimizing overall energy consumption
3Speed
If asynchronous hardware resets are allowed to trigger without persistent flush handler invocation, then the system responds quickly to reset events, but persistent memory state is not properly flushed resulting in data loss or corruption
Solution Approach 1:
The patent implements a preliminary check mechanism that detects asynchronous reset events and proactively determines whether a persistent flush operation is needed before the reset completes. This preliminary action ensures data integrity is maintained while minimizing the delay introduced by the flush operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures the persistent memory state is maintained without relying on BBUs, efficiently using PSU bulk capacitors to complete cache flush operations, even during asynchronous resets, thereby preventing data loss or corruption.
Implementation Method 1
efficiently using PSU bulk capacitors to complete cache flush operations
Data Source
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AI summary
Techniques are described herein processing asynchronous power transition events while maintaining a persistent memory state. In some embodiments, a system may proxy asynchronous reset events through system logic, which generates an interrupt to invoke a special persistent flush interrupt handler that performs a persistent cache flush prior to invoking a hardware power transition. Additionally or alternatively, the system may include a hardware backup mechanism to ensure all resets and power-transitions requested in hardware reliably complete within a bounded window of time independent of whether the persistent cache flush handler succeeds.