Persistent Memory Wear-Leveling via Access Count Tracking
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Solution Overview
Problem
The limited write endurance of storage class memory (SCM) devices in compute service systems leads to premature degradation and data loss, as they are subjected to a high frequency of write operations, which can concentrate on specific blocks, exceeding their write endurance limit and causing errors.
Innovation Solution
An integrated circuit with a cache device that stores mappings between logical and physical addresses and maintains access counts to facilitate wear-leveling operations, distributing write operations more evenly across SCM blocks, and storing statistics logs in persistent memory to support robust wear-leveling policies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write operations are performed frequently on SCM devices to meet high storage capacity and fast access requirements, then productivity and storage performance are improved, but the limited write endurance causes premature degradation and data loss
Solution Approach 1:
The patent segments the SCM device into multiple blocks and implements wear-leveling by distributing write operations across different blocks. The system maintains a mapping table that tracks the number of write operations for each block, allowing it to rotate through blocks in a way that equalizes wear across the entire device, thereby extending overall lifespan while maintaining high write performance.
Solution Approach 2:
The patent changes the parameter of write operation distribution from concentrated to evenly distributed across blocks. By tracking write counts per block and dynamically selecting target blocks based on wear levels, the system transforms the write pattern to prevent any single block from reaching its endurance limit prematurely, thus resolving the contradiction between high write speed and data reliability.
2Device complexity
If write operations are concentrated on specific blocks to simplify address mapping, then device complexity is reduced, but write endurance is exceeded and errors occur
Solution Approach 1:
The SCM device is divided into multiple addressable blocks, each tracked individually in a mapping table. This segmentation allows the system to maintain simple linear address mapping while distributing writes across blocks. The mapping table stores the relationship between logical addresses and physical blocks along with write counts, enabling both simplicity and wear-leveling.
Solution Approach 2:
The system implements feedback by continuously monitoring write operation counts for each block and using this information to dynamically adjust the address mapping. When a block approaches its wear limit, the system redirects new writes to less-worn blocks, ensuring reliability without increasing overall system complexity.
3Reliability
If access counts are maintained for each physical address to enable wear-leveling, then write operation distribution is improved, but volatile memory resources are consumed
Solution Approach 1:
The patent extracts the write count information from the main volatile memory and stores it in a separate, optimized structure within the SCM device itself. This separation allows the wear-leveling metadata to be persisted without consuming valuable volatile memory resources, while still enabling effective wear-leveling operations through the maintained access counts.
Solution Approach 2:
The SCM device maintains its own wear-leveling metadata (access counts per block) internally, making it self-sufficient for wear management. This self-service approach eliminates the need for external volatile memory to store wear information, as the device autonomously tracks and manages its own block wear states.
Data Source
AI summary
Disclosed herein are techniques for management of a non-volatile memory device. In one example, an integrated circuit comprises a cache device and a management controller. The cache device is configured to store a first mapping between logical addresses and physical addresses of a first memory, the first mapping being a subset of mapping between logical addresses and physical addresses of the first memory stored in a second memory, and an access count associated with each of the physical addresses of the first mapping. The management controller is configured to: maintain access statistics of the first memory based on the access counts stored in the cache device; and determine the mapping between logical addresses and physical addresses stored in the second memory based on the access statistics and predicted likelihoods of at least some of the logical addresses receiving an access operation.