Persistent Reset Vector Register for Processor Adaptability
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Solution Overview
Problem
Existing processor systems lack flexibility in resetting and vectoring, as the reset vector address is often hardwired, limiting adaptability to different systems and potentially compromising security by making reset code vulnerable to exploitation.
Innovation Solution
Incorporating a reset vector base address register that can be programmatically updated with a reset vector address, allowing the processor to capture and use a new reset vector address upon reset, even when powered down, and utilizing an always-on logic circuit to persist this address across power cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the reset vector address is hardwired in the processor, then the system achieves predictability and simplicity, but the system loses flexibility and adaptability to different systems
Solution Approach 1:
The reset vector address is made dynamic by introducing a register that can be programmed with different addresses. The register is configured to be updated during system operation, allowing the reset vector address to change from a fixed hardwired value to a programmable value that adapts to different system requirements without requiring physical reconfiguration.
Solution Approach 2:
The patent changes the parameter of the reset vector address from a fixed hardware value to a configurable register value. This allows the address to be modified through software or control signals, enabling the same processor to function in different systems with different reset vector requirements.
2Adaptability or versatility
If the reset vector address is made programmable via a register, then the system achieves flexibility and adaptability, but the system generates potential security vulnerabilities where the reset code becomes exploitable
Solution Approach 1:
The patent implements periodic relocation of the reset vector address by updating the register at different time points during system operation. This periodic changing of the reset vector address prevents attackers from exploiting a fixed, predictable address, as the address changes over time making it difficult to predict or target the reset code location.
Solution Approach 2:
By making the reset vector address dynamic through programmable registers that can be updated during system operation, the system prevents security vulnerabilities associated with fixed addresses. The dynamic nature of the address makes it harder for attackers to predict or exploit the reset code location.
3Productivity
If the reset code is relocated to different memory pages, then the system improves security and memory utilization, but the system increases complexity in managing multiple reset codes and address mappings
Solution Approach 1:
The patent implements a universal register structure that serves multiple functions: it stores the reset vector address, can be programmed with different addresses, and maintains the address across power cycles. This multi-functional register simplifies the overall system architecture compared to having separate mechanisms for each function, while still enabling code relocation for security and memory optimization.
Solution Approach 2:
The register is configured to automatically retain and use the programmed reset vector address across power cycles without requiring external intervention. The system self-manages the address persistence, eliminating the need for complex external memory management mechanisms while still achieving code relocation capabilities.
Data Source
AI summary
In an embodiment, an integrated circuit includes at least one processor. The processor may include a reset vector base address register configured to store a reset vector address for the processor. Responsive to a reset, the processor may be configured to capture a reset vector address on an input, updating the reset vector base address register. Upon release from reset, the processor may initiate instruction execution at the reset vector address. The integrated circuit may further include a logic circuit that is coupled to provide the reset vector address. The logic circuit may include a register that is programmable with the reset vector address. More particularly, in an embodiment, the register may be programmable via a write operation issued by the processor (e.g. a memory-mapped write operation). Accordingly, the reset vector address may be programmable in the integrated circuit, and may be changed from time to time.