Persistent Storage Address Translation Cache Prepopulation for Low-Latency I/O

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Solution Overview

Problem

The latency in operations performed by persistent storage devices is increased due to the need for address translations between virtual machines and the host's operating system, which are performed after receiving input-output commands.

Innovation Solution

The host prepopulates the address translation cache of the persistent storage device with necessary translations before sending input-output commands, allowing the device to perform direct memory access without waiting for translations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If address translation is performed after receiving input-output commands, then address translation accuracy is maintained, but operation latency increases

Engineering Contradiction:
Improveoperation latencyVSAvoidaddress translation speed
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The host prepopulates the address translation cache with address translation entries before the persistent storage device needs to execute input-output commands. This preliminary action ensures that when commands are received, the address translations are already available in the cache, eliminating the need for real-time translation requests and reducing operation latency.

Inventive Principle:
Principle #10Preliminary action

2Speed

If address translation cache is prepopulated before sending input-output commands, then operation speed increases, but system complexity increases

Engineering Contradiction:
Improveinput-output operation speedVSAvoidaddress translation management complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The address translation cache acts as an intermediary between the host's virtual address space and the persistent storage device's physical address space. The host prepopulates this cache with translation entries, and the persistent storage device uses the cache to perform direct memory access without requiring real-time translation requests, thereby simplifying the overall translation management while improving speed.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If direct memory access is performed without waiting for address translation, then productivity increases, but risk of incorrect address access increases

Engineering Contradiction:
Improvedata access efficiencyVSAvoidaddress access accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The host prepopulates the address translation cache with accurate address translation entries before the persistent storage device executes input-output commands. This preliminary population ensures that when direct memory access is performed using the cached translations, the addresses are correct, thereby maintaining reliability while enabling high-speed data access without waiting for real-time translations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4266180B1Systems and methods for address translation
Publication Date: 2025.08.06 SAMSUNG ELECTRONICS CO LTD
  • EP4266180B1 patent drawingFigure 1
  • EP4266180B1 patent drawingFigure 2
  • EP4266180B1 patent drawingFigure 3

AI summary

A system and method for host provided address translation cache prepopulation. In some embodiments, the method includes: receiving, by a persistent storage device, a first address translation cache entry; receiving, by the persistent storage device, an input-output command; and executing the input-output command, by the persistent storage device, the executing of the input-output command including performing direct memory access of a memory location at an address calculated based on the input-output command and based on the first address translation cache entry.