Persistent Store Fence Instruction for Non-Volatile Memory Durability
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Solution Overview
Problem
Current processor instructions, such as SFENCE, do not effectively serialize store operations to persistent storage, leading to potential data loss in case of power failures or system crashes, as they primarily focus on global visibility rather than persistency or durability.
Innovation Solution
The introduction of a persistent store fence instruction that ensures data is stored persistently in non-volatile memory before subsequent store operations, using a persistent store fence buffer to bypass caches and implement write combining, thereby guaranteeing data durability and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SFENCE instruction is used to serialize store operations, then global visibility of stores is guaranteed, but data persistency in non-volatile memory cannot be ensured
Solution Approach 1:
The patent segments the store serialization function into two distinct instructions: SFENCE for global visibility (volatile memory) and PSFENCE for data persistency (non-volatile memory). This segmentation allows each instruction to target specific memory types and achieve its dedicated function without compromising the other, directly resolving the contradiction between global visibility and data persistency.
Solution Approach 2:
The patent introduces a persistent store fence buffer as an intermediary structure between the processor and non-volatile memory. This buffer temporarily holds store data and manages the flushing process to persistent storage, ensuring that data is safely stored before subsequent operations can proceed, thereby guaranteeing data persistency.
2Reliability
If all store operations are serialized to persistent storage, then data durability is guaranteed, but processing latency increases
Solution Approach 1:
The patent applies partial action by having PSFENCE serialize only the specific store operation it targets, rather than all subsequent store operations. This selective serialization reduces the latency impact while still ensuring data durability for the critical store operation, avoiding the excessive latency that would result from serializing all stores.
Solution Approach 2:
The persistent store fence buffer performs preliminary actions by pre-flushing critical data to non-volatile memory before system failures can occur. This preliminary action ensures data durability is established in advance, allowing subsequent store operations to proceed without waiting for persistent storage completion, thereby reducing overall processing latency.
3Productivity
If SFENCE is used for all memory operations, then global visibility is achieved, but efficiency of write-ahead logging and serial store algorithms deteriorates
Solution Approach 1:
The patent applies local quality by making PSFENCE specifically targeted at persistent memory operations rather than all memory operations. This allows write-ahead logging and serial store algorithms to efficiently serialize only the critical persistent store operations that require durability guarantees, while leaving other volatile memory operations unaffected and efficient.
Data Source
AI summary
A processor of an aspect includes a decode unit to decode a persistent store fence instruction. The processor also includes a memory subsystem module coupled with the decode unit. The memory subsystem module, in response to the persistent store fence instruction, is to ensure that a given data corresponding to the persistent store fence instruction is stored persistently in a persistent storage before data of all subsequent store instructions is stored persistently in the persistent storage. The subsequent store instructions occur after the persistent store fence instruction in original program order. Other processors, methods, systems, and articles of manufacture are also disclosed.