Persistent Virtual Routing for Accurate IC Timing Optimization
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Solution Overview
Problem
In modern IC design, predicting interconnect delays and parasitics during the pre-routing stage is inaccurate, leading to over-optimization of non-critical nets and under-optimization of critical ones, causing design convergence issues and inferior IC performance due to the divergence between routing estimates and actual topologies.
Innovation Solution
Implementing persistent virtual routing, where selected nets are guaranteed routes during placement-based optimization, using actual parasitics and delays, and ranking nets based on criteria like slack, fanout, and electrical sensitivity to minimize routability impact and ensure accurate optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If virtual routing is used during pre-route optimization, then routing speed is improved, but routing accuracy deteriorates due to congestion unawareness
Solution Approach 1:
The patent performs preliminary congestion-aware global routing to generate initial routes before detailed routing. These pre-computed routes are stored and reused during placement optimization, eliminating the need for repeated virtual routing computations while maintaining routing accuracy through congestion awareness.
Solution Approach 2:
The patent creates copies of congestion maps and routing data structures that can be efficiently queried during placement optimization without performing full virtual routing computations. These copies preserve the congestion-aware routing information while enabling fast access during iterative optimization.
2Measurement precision
If congestion-aware global routing is performed, then routing accuracy is improved, but computation cost increases significantly
Solution Approach 1:
The patent performs congestion-aware global routing once at the beginning to establish initial routes, then preserves these routes throughout placement optimization. This preliminary action eliminates the need for repeated computationally expensive congestion-aware routing computations during iterative placement steps.
Solution Approach 2:
The patent applies congestion-aware routing selectively to critical nets rather than all nets. By identifying and prioritizing nets with timing constraints or high sensitivity to routing variations, the patent achieves improved routing accuracy for the most important connections while minimizing overall computation cost.
3Productivity
If pre-route optimization is performed with inaccurate delay estimates, then optimization speed is maintained, but optimization quality deteriorates due to over-optimization of non-critical nets
Solution Approach 1:
The patent implements feedback mechanisms where routing results from global routing are fed back into the placement optimization process. This feedback loop provides accurate delay and parasitic information that guides optimization decisions, preventing over-optimization of non-critical nets while maintaining focus on timing-critical paths.
Solution Approach 2:
The patent performs preliminary routing to establish accurate delay estimates before detailed placement optimization. These preliminary routing results serve as the basis for timing-driven placement, enabling quality optimization without requiring repeated expensive re-routing computations.
Data Source
AI summary
A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with route-based delays and parasitics for the selected nets. At this point, synthesis can be run using actual route-based delays and parasitics for the selected nets, with their routes being updated incrementally as needed. In one embodiment, the nets can be re-ranked after synthesis. Finally, these routes can be preserved across the subsequent global routing of the remaining nets.