PFC Bias Circuit for Low Switching Loss at No-Load
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Solution Overview
Problem
Power supplies with power factor correction controllers experience significant switching losses during light or no load conditions, which can exceed 70% of input power and violate energy efficiency standards.
Innovation Solution
A power factor correction bias circuit is introduced to modify the operation of the PFC controller by applying a small DC offset to the current multiplier node, reducing the frequency of switching events and increasing the dead time between bursts, thereby minimizing power expenditure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power factor correction controller operates continuously to maintain unity power factor, then power factor is improved, but switching losses increase significantly under light or no load conditions
Solution Approach 1:
The patent applies periodic action by introducing burst mode operation where the PFC controller operates in intermittent bursts rather than continuously. The controller activates for short periods to maintain output voltage, then enters sleep mode, creating periodic on-off cycles that reduce switching losses while still maintaining power factor correction during active periods.
Solution Approach 2:
The patent implements dynamics by making the PFC controller's operating state variable - transitioning between active burst mode and sleep mode based on load conditions. The controller dynamically adjusts its behavior based on feedback from voltage sensing, allowing it to adapt between continuous operation at full load and periodic operation at light/no load, optimizing the trade-off between power factor maintenance and energy loss.
2Stability of the object's composition
If switching frequency is increased to maintain output voltage stability, then output voltage stability is improved, but switching losses increase
Solution Approach 1:
The patent uses periodic action to maintain output voltage stability through controlled bursts of high-frequency switching followed by sleep periods. During active bursts, the controller switches at high frequency to quickly recharge the output capacitor and maintain voltage, then enters sleep mode where voltage is maintained by capacitor discharge, creating periodic voltage maintenance cycles.
Solution Approach 2:
The patent applies preliminary action by pre-charging the output capacitor to a voltage higher than the nominal output voltage during the active burst phase. This over-charging creates a voltage headroom that allows the capacitor to maintain acceptable output voltage during the subsequent sleep period without requiring continuous switching, thereby reducing overall switching frequency and losses.
Data Source
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AI summary
A system and methods for reducing switching losses during light to no load conditions is presented. Embodiments of the system disclosed herein include a bias circuit that modifies operation of the PFC controller of a power supply to reduce the occurrence of burst operation over time. The reduction in the number of occurrences of the burst operation over a time period when the power supply is operating in a light or no load condition reduces the amount of idle power.