Power Factor Correction Circuit Burst Mode Control

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Solution Overview

Problem

Conventional power factor correction circuits experience efficiency drops and increased switching losses in lightly loaded states, and the PFC circuit's on/off operation complicates designing posterior converters due to varying output voltages.

Innovation Solution

A power factor correction circuit that operates the switching element in a burst mode by performing a weighted addition of input voltage and output voltage, using a control IC to generate a signal for turning the switching element on/off, reducing switching losses and improving efficiency without a coupling capacitor, and incorporating a minimum on-time-width changing circuit for wider pulse widths during standby.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the switching element operates in conventional continuous mode, then the power factor correction function is maintained, but the switching loss increases and efficiency decreases in lightly loaded states

Engineering Contradiction:
Improveswitching lossVSAvoidefficiency
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The patent applies periodic action by implementing burst mode operation where the switching element operates in intermittent bursts rather than continuously. The control circuit generates burst signals that activate the switching element only during specific intervals, allowing it to remain off during other intervals. This periodic activation reduces the total number of switching operations per unit time, thereby decreasing switching losses and improving efficiency in lightly loaded states while maintaining the power factor correction function.

Inventive Principle:
Principle #19Periodic action

2Productivity

If the PFC circuit operates in burst mode to reduce switching loss, then efficiency improves, but the output voltage varies which complicates designing posterior converters

Engineering Contradiction:
ImproveefficiencyVSAvoidoutput voltage stability
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The patent implements feedback control by incorporating a control circuit that monitors the output voltage of the PFC circuit and adjusts the burst mode operation accordingly. The control circuit compares the actual output voltage with a reference voltage and modifies the burst signaling to maintain stable output voltage despite the intermittent switching operation. This feedback mechanism ensures that the output voltage remains stable for posterior converters while still achieving the efficiency benefits of burst mode operation.

Inventive Principle:
Principle #23Feedback

3Device complexity

If conventional PFC control is used, then the circuit operation is simple, but the number of external components increases due to requiring coupling capacitors

Engineering Contradiction:
Improvenumber of external componentsVSAvoidcircuit integration
Core Design Contradiction:
Device complexityVSEase of manufacture

Solution Approach 1:

The patent applies merging by integrating the coupling capacitor function directly into the control IC through an internal capacitor. Instead of requiring separate external coupling capacitors, the control IC incorporates the necessary capacitance internally to generate the burst signals. This integration eliminates the need for multiple external components, simplifies the circuit design, and makes the PFC circuit more suitable for compact and cost-effective manufacturing while maintaining the required signal coupling functionality.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9859788B2Power factor correction circuit and switching power supply apparatus
Publication Date: 2018.01.02 FUJI ELECTRIC CO LTD
  • US9859788B2 patent drawing
  • US9859788B2 patent drawing
  • US9859788B2 patent drawing

AI summary

When a standby signal is High, a Comp_stb signal that is overlapped with an AC waveform is output from an AC-COMP combining circuit in a COMP signal changing circuit, input into a PWM.comp, and compared with an output waveform of a ramp oscillator. Here, only when a peak of the Comp_stb signal is higher than a minimum voltage of the ramp oscillator is an OUT terminal output signal output from a control IC and a burst operation is performed. When the Comp_stb signal is lower than the minimum voltage of the ramp oscillator, the OUT terminal output signal is not output from the control IC because a reset signal of an RSFF remains High. Accordingly, a switching loss is reduced by operating a switching element in a burst mode when a switching power supply apparatus is in a lightly loaded or unloaded state.