PFC Controller Offset Setting for Low-Voltage Harmonic Suppression
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Solution Overview
Problem
Existing power factor correction circuits struggle to maintain a high power factor by accurately aligning the phase of AC input voltage and current, leading to distortions and inefficiencies, particularly at low input voltages.
Innovation Solution
The implementation of an offset voltage generation circuit within the power factor correction circuit, which adjusts the on-time of the switching transistor based on an offset voltage, ensuring proper discharge of capacitors and smooth current output even at low input voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional power factor correction circuits are used, then the power factor can be improved under normal operating conditions, but total harmonic distortion increases and performance deteriorates at low input voltages
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal switching timings for the switching transistor across different input voltage ranges in a lookup table before operation. During runtime, the controller simply retrieves the pre-determined switching timing based on the current input voltage level, avoiding real-time calculation complexities and ensuring optimal performance across all voltage conditions including low input voltages where conventional circuits fail
Solution Approach 2:
The patent changes the control parameter from fixed switching timing to variable switching timing that adapts to different input voltage levels. By dividing the operating range into multiple voltage levels and assigning different switching timings to each level, the system optimizes the power factor and minimizes harmonic distortion across the entire operating range, particularly improving performance at low input voltages
2Reliability
If switching timing is optimized for high power factor, then power factor improves, but circuit complexity increases
Solution Approach 1:
The patent uses a lookup table that stores pre-calculated switching timings for different input voltage levels. Instead of implementing complex real-time optimization algorithms, the controller copies the appropriate switching timing from the lookup table based on the current voltage level, achieving optimal power factor correction with minimal computational complexity and simpler hardware requirements
Data Source
AI summary
A controller configured to control a power factor correction (PFC) circuit including a DC/DC converter, includes: a first external terminal receiving a full-wave rectified first voltage; a second external terminal receiving a first detection voltage generated by a current flowing through a sense resistor connected to a ground potential; an error amplifier circuit generating a second voltage by amplifying an error between a second detection voltage corresponding to the DC/DC converter's output voltage and a reference voltage; an arithmetic circuit generating a third voltage by multiplying the first and second voltages; an inverting amplifier generating a fourth voltage from the first detection voltage; a comparator comparing the third and fourth voltages; and a drive circuit driving a switching element in the PFC circuit to be turned on or off such that the switching element is turned off each time the fourth voltage becomes higher than the third voltage.