PFC Controller Phase-Shifted Cycle Generation
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Solution Overview
Problem
Existing PFC controllers for interleaved switching regulators are complex and large, with accuracy influenced by process variations, and unable to control varying on-off operation frequencies of switching elements.
Innovation Solution
A semiconductor integrated circuit PFC controller that generates switch control signals with phase-shifted cycles using counters and registers to control switching elements in parallel voltage step-up chopper circuits, allowing for variable on-duty and frequency control while reducing harmonic components and current ripple.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing PFC controller designs are used, then phase-shifted control can be achieved, but the circuit scale becomes large and complexity increases
Solution Approach 1:
The oscillator generates a single clock signal that serves multiple functions: it provides the timing basis for both the master switch control and the slave switch phase-shifted control, and it enables variable frequency operation for both channels simultaneously. This multi-functional clock signal approach eliminates the need for separate oscillators and reduces circuit complexity while maintaining phase-shifted control capability.
Solution Approach 2:
The patent combines the master switch control circuit and slave switch control circuit into a single integrated PFC controller chip. The control logic for generating phase-shifted gate signals is merged into unified control circuits that share common resources such as the oscillator and clock distribution network, thereby reducing overall circuit scale and component count.
2Ease of operation
If existing PFC controller designs are used, then switching control can be implemented, but overall accuracy is influenced by process variation
Solution Approach 1:
The patent replaces analog timing and phase-shift control mechanisms with digital counter-based control. The slave switch phase shift is achieved by counting clock cycles in a digital counter, which is then used to gate the slave switch control signal. This digital approach is less sensitive to process variations in capacitor values and resistor tolerances compared to analog RC timing circuits, thereby improving operational accuracy.
3Device complexity
If fixed frequency control is used, then simple control logic can be implemented, but variable on-off operation frequency control is not possible
Solution Approach 1:
The patent implements dynamic frequency control by making the oscillator frequency variable through control voltage adjustment. The oscillation frequency is dynamically changed based on feedback from the output voltage or current, allowing the PFC controller to adapt to different operating conditions and load requirements while maintaining simple control logic through automated feedback loops.
Data Source
AI summary
A PFC counter which controls a switching element of voltage step-up chopper circuits arranged in parallel has a circuit (SLOG) generating a switch signal (GD_S) whose phase is shifted from that of a switch signal of one of the switching elements. This circuit has a first counter (COUNTM) which counts clock signals by a cycle unit of one of the switch signals; a second counter (COUNTS) which counts clock signals by a cycle unit having a predetermined phase difference with respect to one of the switch signals; and a first register (REG1) which holds a value counted by the first counter corresponding to a high-level period of one of the switch signals.