PFC Operating Windows for Low Load Efficiency

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Solution Overview

Problem

Switched mode power supplies with power factor correction (PFC) stages face efficiency degradation at light loads due to high switching frequency and increased switching losses, particularly near zero crossing of the AC waveform, leading to significant energy waste and power factor deterioration.

Innovation Solution

The method involves defining operating windows within the AC half-cycle and controlling the switching frequency and on-time to optimize efficiency, with the window positioned around the peak of the AC supply to minimize losses and maintain high power factor, using a control circuit that adjusts the width of the operating window based on output characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If switching is performed throughout the entire AC half-cycle to maintain continuous power factor correction, then the power factor is improved, but switching losses increase significantly near zero crossing leading to efficiency degradation

Engineering Contradiction:
Improvepower factorVSAvoidswitching losses
Core Design Contradiction:
Object-generated harmful factorsVSLoss of energy

Solution Approach 1:

The patent divides the AC half-cycle into multiple operating windows (first, second, third windows) with different switching frequency characteristics. The first operating window near zero crossing uses reduced switching frequency or skipped cycles, while subsequent windows use normal switching frequency. This segmentation allows the system to maintain power factor correction across the entire half-cycle while avoiding excessive switching losses in the problematic zero-crossing region.

Inventive Principle:
Principle #1Segmentation

2Object-generated harmful factors

If switching frequency is increased to improve power factor correction performance, then the power factor is improved, but switching losses increase leading to efficiency degradation at light loads

Engineering Contradiction:
Improvepower factorVSAvoidswitching losses
Core Design Contradiction:
Object-generated harmful factorsVSLoss of energy

Solution Approach 1:

The patent implements dynamic adjustment of switching frequency based on the instantaneous AC voltage level and operating window position. The control system varies the switching frequency throughout the half-cycle, using lower frequencies near zero crossing and higher frequencies in subsequent windows. This dynamic approach allows the power factor correction to adapt to changing conditions, maintaining effectiveness while minimizing switching losses at each moment.

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If the PFC circuit operates at boundary conduction mode to achieve good regulation, then output voltage control is improved, but efficiency degrades at light loads due to high switching frequency

Engineering Contradiction:
Improveoutput voltage controlVSAvoidefficiency
Core Design Contradiction:
Measurement precisionVSLoss of energy

Solution Approach 1:

The patent applies different operational characteristics to different portions of the AC cycle. In the first operating window near zero crossing, the system uses reduced switching frequency or skipped cycles, while in subsequent windows it maintains boundary conduction mode operation. This local differentiation allows the PFC to achieve good voltage regulation during the majority of the cycle while avoiding efficiency penalties during the problematic zero-crossing region.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP2387817B1PFC with high efficiency at low load
Publication Date: 2018.06.27 NXP BV
  • EP2387817B1 patent drawingFigure 1
  • EP2387817B1 patent drawingFigure 2~3
  • EP2387817B1 patent drawingFigure 4~6

AI summary

A Power Factor Corrector (PFC), typically used as the first stage of switched mode power supplies, particularly suited for Universal Mains inputs, is disclosed, along with methods for controlling a switched mode power supply having power factor correction. In order to increase efficiency, particularly under low load conditions, without undue degradation of the Power Factor, the switching of the PFC circuit is confined to one or more operating windows within each half-cycle. In embodiments, the operating window comprises a small time window centred around the peak of the mains voltage. The higher the power level, the wider the switching window.