PFC Signal Generation Circuit Phase Difference Adjustment
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Solution Overview
Problem
In PFC control systems, detecting zero current in both coil currents can lead to phase differences between PFC control pulse signals becoming excessively small or large due to noise, causing increased power loss and reduced power factor.
Innovation Solution
A PFC signal generation circuit that adjusts the timing of turning on switches based on zero current detection in inductors, ensuring a target phase difference by waiting until a target timing or the next cycle, depending on the zero current detection timing of the second inductor, to generate PFC control pulse signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If zero current detection is performed in both coil currents to generate PFC control pulse signals, then the critical mode for both coil currents can be ensured improving efficiency, but the phase difference between PFC control pulse signals becomes excessively small or large due to noise causing increased power loss and reduced power factor
Solution Approach 1:
A phase difference adjustment circuit is introduced as an intermediary between the zero current detection circuits and the PFC control pulse signal generation. This circuit receives the detected zero current timings and adjusts the phase difference of the generated PFC control pulse signals to maintain a predetermined relationship, thereby preventing excessive phase deviation caused by noise while ensuring both coil currents operate in critical mode.
Solution Approach 2:
The system implements feedback by detecting the zero current timings in both coil currents and using this information to adjust the phase difference of the PFC control pulse signals. The phase difference adjustment circuit continuously monitors and corrects the phase relationship based on the detected timings, creating a closed-loop control system that maintains stable operation despite noise interference.
2Loss of energy
If zero current detection is performed in both coil currents to generate PFC control pulse signals, then the critical mode for both coil currents can be ensured improving efficiency, but the power factor is reduced due to abnormal phase differences
Solution Approach 1:
The phase difference adjustment circuit serves as a mediator that ensures the PFC control pulse signals maintain the correct phase relationship required for optimal power factor. By adjusting the phase difference based on detected zero current timings, the circuit prevents abnormal phase shifts that would degrade power factor while still enabling critical mode operation in both coils.
3Power
If PFC control pulse signals with phase difference π are generated to achieve interleave mode operation, then electric power twice as large as single mode is obtained, but noise causes the phase difference to deviate from the target value
Solution Approach 1:
The system uses feedback from zero current detection to continuously monitor and adjust the phase difference of PFC control pulse signals. By detecting the actual zero current timings and comparing them against the target phase difference of π, the phase difference adjustment circuit corrects any deviations caused by noise, ensuring accurate interleave mode operation while maintaining doubled power output.
Solution Approach 2:
The phase difference adjustment circuit performs preliminary adjustment of the PFC control pulse signal timing based on predicted optimal phase relationships. By proactively adjusting the phase difference before noise can cause significant deviation, the system maintains accurate timing for interleave mode operation, ensuring both coils operate at maximum power with correct phase relationship.
Data Source
AI summary
A PFC signal generation circuit which generates a PFC signal to control a PFC circuit including a first inductor connected to a first switch and a second inductor connected to a second switch includes: a first control signal output circuit that outputs a first PFC signal to turn on the first switch at a zero current detection timing of the first inductor; a timing adjustment circuit that generates a control signal to turn on the second switch after waiting until a target timing, when a zero current detection timing of the second inductor is earlier than the target timing, and to turn on the second switch at a target timing in a subsequent cycle, when it is later than an allowable period from the target timing; and a second control signal output circuit that generates a second PFC signal to turn on the second switch according to a control signal.