PFC Zero Current Detection Circuit Noise Filtering

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Solution Overview

Problem

Existing power factor correction (PFC) systems face challenges in accurately detecting zero current in PFC inductors due to noise interference from DC/DC converters, leading to false detections and inefficient operation, resulting in poor power factor, high harmonic distortion, and increased noise.

Innovation Solution

A PFC controller zero current detection circuit is developed, incorporating a differentiator circuit, window comparator, ringing qualification circuit, and flip-flop to distinguish between noise and idle ringing in the drain voltage, ensuring accurate detection of zero current in the inductor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If noise filtering is applied to detect zero current in PFC inductor, then false detections are reduced, but detection response time increases and system complexity increases

Engineering Contradiction:
Improvezero current detection accuracyVSAvoiddetection circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The detection circuit is segmented into distinct functional blocks: a differentiator circuit for rate-of-change detection, a comparator for threshold evaluation, and a timer circuit for validation. This segmentation allows each block to perform a specific function, improving overall detection reliability while keeping individual blocks simple and manageable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A timer circuit is introduced as an intermediary element between the comparator and the zero current detection output. The timer validates the comparator's output by checking whether the rate-of-change condition persists for a predetermined time period, thereby filtering out noise-induced false detections while maintaining responsive detection through configurable timing.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If simple voltage threshold detection is used, then circuit complexity is reduced, but noise from DC/DC converter causes false zero current detections

Engineering Contradiction:
Improvedetection circuit complexityVSAvoidzero current detection accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

Instead of using a simple voltage threshold, the system monitors the rate of change of the drain voltage (dV/dt). This parameter transformation converts the detection criterion from absolute voltage level to temporal variation, enabling the circuit to distinguish between noise (random fluctuations) and genuine zero current events (systematic voltage transitions), thereby improving detection accuracy without excessive complexity.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If PFC operates in continuous conduction mode to improve power factor, then harmonic distortion is reduced, but zero current detection becomes unreliable due to noise

Engineering Contradiction:
Improvepower factor correction performanceVSAvoidzero current detection precision
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The timer circuit provides feedback validation to the zero current detection process. By requiring that the rate-of-change condition be sustained for a predetermined time period before confirming zero current, the system creates a feedback mechanism that filters out spurious detections caused by noise, ensuring reliable operation in continuous conduction mode where zero current intervals are brief and easily obscured by noise.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10673322B1Power factor correction zero current detection
Publication Date: 2020.06.02 TEXAS INSTRUMENTS INC
  • US10673322B1 patent drawing
  • US10673322B1 patent drawing
  • US10673322B1 patent drawing

AI summary

A power factor correction controller zero current detection circuit includes a differentiator circuit, a comparator, a first qualification timer circuit, an idle ringing detector circuit, a second qualification timer circuit, and a flip-flop. The comparator is coupled to the differentiator circuit. The first qualification timer circuit includes an input coupled to an output of the comparator. The idle ringing detector circuit includes a first input coupled to the output of the comparator, and a second input coupled to an output of the first qualification timer circuit. The second qualification timer circuit includes a first input coupled to the output of the first qualification timer circuit, and a second input coupled an output of the idle ringing detector circuit. The flip-flop includes a first input coupled to the output of the comparator, and a second input coupled to an output of the second qualification timer circuit.