PFD and Charge Pump Gain Boosting for Fast-Locking PLLs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Phase lock loop (PLL) circuits face challenges in reducing locking time without increasing circuit area or sacrificing noise and frequency performance, particularly in integer-N and fractional-N applications.
Innovation Solution
The implementation of a phase frequency detector (PFD) system with flip-flops, delay elements, and gated core circuits that provide delayed pulses to enhance gain, along with a programmable feedback divider and charge pump for fast-locking capabilities, allowing for reduced locking time without significant area expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If charge pump current is increased by a factor of N to reduce locking time, then locking time is reduced, but circuit area increases significantly
Solution Approach 1:
The PFD is divided into multiple parallel paths, each with its own flip-flop and delay element. Instead of using a single high-current charge pump, the patent segments the detection function across multiple parallel PFD paths that can operate simultaneously, distributing the gain enhancement across multiple lower-current paths rather than concentrating it in one high-current path.
Solution Approach 2:
The patent introduces a temporal dimension by using delay elements to create multiple delayed versions of the reference and feedback signals. These delayed signals are processed through parallel PFD paths, effectively adding a time-based dimension to the phase detection process. This allows gain enhancement through time-multiplexed parallel processing rather than spatial expansion of high-current circuitry.
2Loss of time
If charge pump gain is boosted to reduce locking time, then locking time is reduced, but noise performance deteriorates
Solution Approach 1:
The total gain requirement is segmented across multiple parallel PFD paths, each contributing a portion of the total gain. This distribution prevents any single path from requiring excessive current that would generate noise, while the combined effect of multiple paths achieves the necessary overall gain for fast locking.
Solution Approach 2:
Each parallel PFD path is optimized with specific delay elements and flip-flop configurations tailored to its function. The delay elements are strategically placed to create optimal phase relationships in each path, allowing each local segment to contribute maximally to the overall gain without requiring uniform high-current design across the entire circuit.
3Loss of time
If loop filter zero-resistor is reduced by sqrt(N) to reduce locking time, then locking time is reduced, but frequency breadth limitations worsen
Solution Approach 1:
The frequency tracking function is segmented across multiple parallel PFD paths, each capable of detecting phase differences at different frequencies. This parallel architecture allows the PLL to maintain broader frequency coverage while achieving fast locking, as each path can operate effectively across a wide frequency range without requiring aggressive loop filter modifications that would limit bandwidth.
4Loss of time
If PFD and CP gains are increased to reduce locking time, then locking time is reduced, but device complexity increases
Solution Approach 1:
Multiple PFD paths are merged into a single unified output that drives one charge pump. The parallel processing paths are combined at the output stage, allowing the system to benefit from the gain enhancement of multiple paths while maintaining a single charge pump interface, thereby reducing complexity compared to having separate charge pumps for each path.
Solution Approach 2:
The delay elements and flip-flops are designed as universal building blocks that can be replicated and configured for different delay requirements. This modular, multi-functional approach allows the same basic circuit topology to serve multiple functions across different parallel paths, reducing overall device complexity through component reuse and standardization.
Data Source
AI summary
The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.