Phase-Frequency Detector Circuit With Delayed Reset for Lower PLL Noise
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Solution Overview
Problem
Conventional Phase-Frequency Detector (PFD) circuits in Phase-Locked Loops (PLLs) contribute significantly to the in-band phase noise floor, and increasing charge pump current to improve gain leads to increased power consumption and noise, limiting the tuning range of Voltage-Controlled Oscillators (VCOs).
Innovation Solution
The proposed PFD circuit design introduces a modified transfer function by adding delay elements and additional logic gates to allow both current sources to operate simultaneously for small phase errors, effectively doubling the gain without increasing charge pump current, thereby reducing system noise and expanding the VCO's tuning range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If charge pump current is increased to improve PFD gain, then gain is improved, but power consumption and noise increase
Solution Approach 1:
The patent segments the charge pump operation into two independent current sources (first and second current sources) that can operate simultaneously. This segmentation allows the PFD to achieve doubled gain (2×ICP) without increasing the current through a single charge pump transistor, thereby avoiding the noise and power consumption penalties associated with higher single-source current operation.
Solution Approach 2:
The patent merges the operation of two current sources in parallel to achieve the desired gain. By allowing both current sources to contribute to the output simultaneously under certain conditions (when both flip-flops are reset), the system achieves doubled gain without requiring a single high-current source that would generate excessive noise and power consumption.
2Power
If charge pump current is increased to improve gain, then gain is improved, but voltage headroom decreases
Solution Approach 1:
The patent segments the gain generation function across two separate current sources operating in parallel. This allows the system to achieve doubled gain (2×ICP) while maintaining the same individual current levels, thereby preserving voltage headroom that would otherwise be consumed by a single high-current source.
3Power
If charge pump current is increased to improve gain, then gain is improved, but power consumption increases
Solution Approach 1:
The patent segments the gain function across two current sources that operate simultaneously but at moderate current levels. This achieves doubled gain (2×ICP) without requiring a single high-current source, thereby reducing power consumption compared to conventional approaches that would require ICP to be doubled to achieve the same gain.
Solution Approach 2:
The patent employs periodic switching of the two current sources based on the phase detection state. The first current source operates during certain phase conditions while the second operates during others, with both capable of simultaneous operation during reset conditions. This periodic allocation allows efficient use of power while maintaining doubled gain capability.
Data Source
AI summary
A phase-frequency detector (PFD) circuit is disclosed. The PFD circuit includes a PFD portion adapted to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference and a delay and reset portion adapted to delay the generated control signals, to generate reset signals for resetting the PFD portion based on a combination of the control signals and the delayed control signals, and to provide the generated reset signals to the PFD portion.