Phase Frequency Detector Clock Edge Blocking for Faster PLL Lock
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Solution Overview
Problem
Conventional Phase Frequency Detectors (PFDs) suffer from nonzero reset delay, leading to reduced operating speed and potential failure in acquiring frequency lock due to gain reversal and missing edge issues, which limit their linear range and cause non-ideal behavior.
Innovation Solution
The implementation of control circuitry that detects missing edges of reference and feedback clocks, generating blocking signals to block the next rising edges of the opposite clock, effectively increasing the positive gain of the Phase Frequency Detector and enhancing the speed of frequency acquisition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If conventional Phase Frequency Detector is used with nonzero reset delay, then the circuit can guarantee minimum pulse width, but the linear range is reduced to less than 4π and non-ideal behavior occurs
Solution Approach 1:
The patent applies preliminary action by detecting missing edges before they cause gain reversal. The control circuitry identifies when a clock edge is missing and proactively blocks subsequent rising edges of the opposite clock, preventing the non-ideal behavior from occurring in the first place. This resolves the contradiction by maintaining the minimum pulse width guarantee while extending the linear range beyond 4π.
2Stability of the object's composition
If nonzero reset delay is implemented in PFD, then minimum pulse width is guaranteed, but operating speed is limited
Solution Approach 1:
The patent implements feedback by using the output of the PFD to control the blocking of clock edges. The control circuitry monitors the UP and DOWN signals and uses this feedback information to determine when to block rising edges, thereby optimizing the operating speed while maintaining stable minimum pulse width through the established feedback mechanism.
3Device complexity
If conventional PFD operation is used, then circuit simplicity is maintained, but gain reversal occurs periodically during PLL lock-in process
Solution Approach 1:
The patent introduces an intermediary control circuitry between the PFD and the clock signals. This intermediary component detects missing edges and generates blocking signals without significantly increasing overall system complexity. The mediator prevents gain reversal by blocking problematic clock edges, thereby improving frequency acquisition reliability while maintaining relative circuit simplicity.
4Productivity
If blocking signals are generated to block next rising edges, then positive gain is increased and frequency acquisition speed is enhanced, but additional control circuitry is required
Solution Approach 1:
The patent applies universality by designing control circuitry that performs multiple functions: detecting missing edges, generating blocking signals, and preventing gain reversal. This multi-functional approach increases frequency acquisition speed while minimizing the additional complexity by consolidating control functions into a single integrated circuit block that handles multiple tasks efficiently.
Data Source
AI summary
Systems and methods herein may include or involve control circuitry that detects missing edges of reference and/or feedback clocks and may block the next N rising edges of the feedback clock or reference clock, respectively. In some implementations, a phase frequency detector (PFD) circuit comprises first circuitry including an output that outputs a missing edge signal. The first circuitry may include components arranged to detect a missing rising edge of one or both of a reference clock signal and a feedback clock signal. Second circuitry is coupled to the first circuitry and may include components arranged to generate one or both of a reference clock blocking signal and a feedback clock blocking signal based on the missing edge signal. Further, in some implementations, the blocking of the next N rising edges of the opposite clock may effectively increase the positive gain of the PFD.