PFD Frequency Doubler Using Rising-Edge-Only Delay Control
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Solution Overview
Problem
Conventional frequency doubling circuits require very linear and fine resolution delay cells for both rising and falling edge delays, which are challenging and costly to design or implement, especially since current delay cells are mostly effective for only one type of edge delay.
Innovation Solution
A phase frequency detector (PFD)-based rising-edge-delay-only frequency doubler circuit is designed, utilizing multiple delay stages and PFDs to implement adjustable delay cells that apply delays only to rising edges, with a comparator controlling the delays based on DC voltage comparisons to achieve accurate frequency doubling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional delay cells are used for both rising and falling edge delays, then frequency doubling accuracy is maintained, but design complexity and cost increase significantly
Solution Approach 1:
The patent segments the frequency doubling function into two independent parts: rising edge delay and falling edge delay. By using separate delay cells for each edge type, the complex requirement of designing a single delay cell that handles both edges with high precision is divided into two simpler, specialized delay cells. This segmentation reduces design complexity while maintaining overall frequency doubling accuracy.
Solution Approach 2:
The patent extracts the rising edge delay function from the conventional dual-edge delay cell and implements it as a separate rising-edge-delay-only cell. This extraction allows the rising edge delay to be optimized independently without the constraints of also handling falling edges, thereby reducing the overall design complexity while preserving frequency doubling performance.
2Device complexity
If specialized delay cells for single edge type are used, then design complexity is reduced, but frequency doubling performance may be compromised
Solution Approach 1:
The patent implements a feedback mechanism where the output of the PFD is fed back to control the delay cells. This feedback loop continuously monitors the phase difference between the input and output signals and adjusts the delay amounts dynamically to maintain optimal frequency doubling performance. The feedback ensures that even with simplified single-edge delay cells, the overall system reliability and performance are preserved.
Solution Approach 2:
The patent uses dynamic delay adjustment where the delay amounts for rising and falling edges are not fixed but are continuously adjusted based on the phase error detected by the PFD. This dynamic adaptation allows the simplified delay cells to compensate for their inherent limitations and maintain high frequency doubling performance through real-time optimization.
Data Source
AI summary
Certain aspects of the present disclosure generally relate to techniques and apparatus for doubling the frequency of a signal. For example, certain aspects are directed to a phase frequency detector (PFD)-based rising-edge-delay-only frequency doubling circuit. One example frequency doubler circuit generally includes a first delay stage, a second delay stage, a first PFD, a first rising-edge-only adjustable delay cell, a second PFD, a second rising-edge-only adjustable delay cell a logic gate, and a comparator configured to compare a direct-current (DC) voltage value of an output of the logic gate with a reference voltage and control the first and second rising-edge-only adjustable delay cells based on the comparison.