Phase-Frequency Detector Logic for Non-Integer PLL Ratios
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing phase locked loop (PLL) circuits face challenges in efficiently handling wide ranges of reference frequencies, requiring additional circuitry that increases complexity, space requirements, and debugging difficulties, especially when dealing with differential signals.
Innovation Solution
A phase-frequency detection (PFD) circuit is configured to double the frequency of a reference signal and generate a direction indication signal to correct phase and frequency errors, using a feedback loop with programmable dividers and flip-flop circuits to achieve non-integer frequency ratios without separate frequency doublers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If frequency dividers or multipliers are added to handle wide reference frequency ranges, then the reference frequency handling capability is improved, but the circuit complexity and space requirements increase
Solution Approach 1:
The patent combines the frequency doubling function with the phase-frequency detection function into a single integrated circuit. The PFD circuit performs both phase detection and frequency doubling by detecting both rising and falling edges of the reference signal, eliminating the need for a separate frequency doubler circuit and reducing overall system complexity
Solution Approach 2:
The PFD circuit is designed to perform multiple functions: phase detection, frequency detection, and frequency doubling. By making the PFD multi-functional, the patent reduces the total number of components needed and simplifies the overall circuit architecture while maintaining the ability to handle wide reference frequency ranges
2Adaptability or versatility
If additional circuitry is added to handle differential signals, then the signal compatibility is improved, but the space requirements and manufacturing complexity increase
Solution Approach 1:
The patent integrates differential signal handling capabilities directly into the PFD circuit structure. The circuit uses complementary metal-oxide-semiconductor (CMOS) technology to natively support differential inputs, combining signal conditioning and phase detection in one unit, thereby reducing manufacturing steps and complexity
3Adaptability or versatility
If separate frequency doublers are added to achieve non-integer frequency ratios, then the frequency synthesis flexibility is improved, but the device complexity and debugging difficulty increase
Solution Approach 1:
The patent merges the frequency doubling operation into the core PFD logic, where the detector naturally generates two output pulses per reference cycle by detecting both edges. This integrated approach enables non-integer frequency ratios through the feedback divider without requiring external frequency doubling stages, simplifying the overall frequency synthesis architecture
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Aspects are directed to an arrangement of circuits configured to generate and correct an output signal relative to a reference signal in response to a direction indication signal. Included in the arrangement of circuits is a phase-frequency detection circuit having logic circuitry configured to respond to the reference signal and a feedback signal by generating and updating the direction indication signal as a function of the logic states of an internal clock signal having risen and fallen. In this context, the feedback signal is generated by a feedback circuit in response to the output signal.