Phase Frequency Detector Pulse-Width Limiting for Smaller Loop Filters
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Solution Overview
Problem
Conventional phase frequency detectors in phase-locked loops face challenges with large circuitry area and volume due to the need for a large capacitor to suppress jitter, especially as the frequency of the reference signal decreases, leading to increased loop bandwidth and limited output pulse width.
Innovation Solution
A phase frequency detector design incorporating edge detectors, latch units, delay units, combination logic, and logic units to generate control signals, which limits the output pulse width by performing logical operations on detection signals, reducing the required capacitance in the loop filter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the loop bandwidth is lowered to maintain stability as reference signal frequency decreases, then loop stability is improved, but a large capacitor is required which increases circuitry area and volume
Solution Approach 1:
The patent changes the temporal parameter of the output pulse width generated by the phase frequency detector. By limiting the maximum width of output pulses, the patent modifies the frequency spectrum characteristics of the loop filter input, allowing the use of smaller capacitors while maintaining the same level of jitter suppression and loop stability.
Solution Approach 2:
The patent applies preliminary action by pre-limiting the output pulse width before it reaches the loop filter. The phase frequency detector inherently constrains its output pulse duration, which proactively prevents the need for large capacitors downstream in the loop filter, thereby reducing overall circuit area while maintaining stability.
2Object-affected harmful factors
If the loop bandwidth is lowered to suppress jitter, then jitter suppression is improved, but the required capacitance increases leading to larger circuit volume
Solution Approach 1:
The patent changes the temporal parameter of the output pulse width generated by the phase frequency detector. By limiting the maximum width of output pulses, the patent modifies the frequency spectrum characteristics of the loop filter input, allowing the use of smaller capacitors while maintaining the same level of jitter suppression and loop stability.
3Measurement precision
If conventional phase frequency detector output pulse width is not limited, then detection accuracy is maintained, but output pulse width becomes large requiring larger capacitance for jitter suppression
Solution Approach 1:
The patent changes the temporal parameter of the output pulse width generated by the phase frequency detector. By limiting the maximum width of output pulses, the patent modifies the frequency spectrum characteristics of the loop filter input, allowing the use of smaller capacitors while maintaining the same level of jitter suppression and loop stability.
Solution Approach 2:
The patent applies preliminary action by pre-limiting the output pulse width before it reaches the loop filter. The phase frequency detector inherently constrains its output pulse duration, which proactively prevents the need for large capacitors downstream in the loop filter, thereby reducing overall circuit area while maintaining stability.
Data Source
AI summary
Phase frequency detectors with limited output pulse width and related methods are disclosed. The proposed phase frequency detector generates a first output signal and a second output signal corresponding to phase difference or frequency difference between a first signal and a second signal. When the phase difference between the first and second signals is greater than a predetermined delay, the pulse width of the first output signal is limited, so that the proposed phase frequency detector has a limited equivalent output pulse width.