Phase-Frequency Detector Logic for Reference Clock Doubling
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Solution Overview
Problem
Existing frequency synthesizer circuits face challenges in efficiently generating spectrally clean high-frequency clocks with non-integer division ratios, requiring additional circuitry that increases complexity and design time, and struggles with differential signal management.
Innovation Solution
A Phase-Frequency Detector (PFD) circuit is configured to double the frequency of the reference signal and generate a direction indication signal to correct phase and frequency errors, eliminating the need for additional circuitry and optimizing signal processing within the PFD circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If additional frequency doubling circuits are added to the reference clock path, then the frequency multiplication capability is improved, but the circuit complexity and design time increase
Solution Approach 1:
The patent combines the frequency doubling function with the PFD circuit by configuring the PFD to respond to both rising and falling edges of the reference clock signal. This integration eliminates the need for separate frequency doubling circuits while maintaining the frequency multiplication capability, thereby reducing circuit complexity and design time.
Solution Approach 2:
The PFD circuit is designed to perform multiple functions: it detects phase differences between the reference clock and feedback clock signals, and simultaneously achieves frequency doubling by responding to both rising and falling edges of the reference clock. This multi-functionality removes the need for dedicated frequency doubling circuitry.
2Speed
If additional frequency doubling circuits are added, then frequency multiplication is achieved, but the validation and debugging difficulty increases
Solution Approach 1:
By merging the frequency doubling function into the PFD circuit itself, the patent reduces the number of separate components that need to be validated and debugged. The integrated approach simplifies the verification process as there are fewer interconnections and components to test, thereby reducing validation and debugging difficulty.
3Adaptability or versatility
If the reference frequency range is widened, then the system adaptability is improved, but consistent PLL performance becomes difficult to maintain
Solution Approach 1:
The patent employs dynamic frequency division ratios in the feedback path that can be adjusted based on the reference frequency. This dynamic adjustment allows the system to maintain consistent PLL performance across a wide range of reference frequencies by adapting the division ratio to match the input frequency, thereby resolving the contradiction between adaptability and performance consistency.
Data Source
AI summary
Aspects are directed to an arrangement of circuits configured to generate and correct an output signal relative to a reference signal in response to a direction indication signal. Included in the arrangement of circuits is a phase-frequency detection circuit having logic circuitry configured to respond to the reference signal and a feedback signal by generating and updating the direction indication signal as a function of the logic states of an internal clock signal having risen and fallen. In this context, the feedback signal is generated by a feedback circuit in response to the output signal.