Phase Frequency Detector Timing Paths for Dead Zone Mitigation
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Solution Overview
Problem
Phase frequency detectors (PFDs) face a dead zone issue where they fail to detect small phase differences, leading to increased phase errors in phase locked loops, and attempts to mitigate this by inserting delays result in missed signal detection and reduced operational range.
Innovation Solution
The implementation of a PFD with independently configurable reset and output processing paths, allowing for decoupling of reset signal and overlap pulse generation paths to minimize reset pulse width and control output signal width, thereby expanding the operational range without affecting dead zone mitigation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a delay is inserted in the PFD to generate a wider PFD output signal to overcome the dead zone, then the dead zone is mitigated, but the width of the reset pulse increases which causes the PFD to miss detection of the reference signal or feedback signal, thereby reducing the operational range
Solution Approach 1:
The patent segments the processing paths into two independent paths: a reset processing path with reset delay to control reset pulse width, and an output processing path with output delay to control output signal width. This segmentation allows each path to be optimized independently, resolving the contradiction between dead zone mitigation and operational range maintenance.
Solution Approach 2:
The patent introduces independently configurable delays in the reset processing path and output processing path, making the system dynamic and adaptable. The reset delay can be adjusted to minimize reset pulse width for maintaining operational range, while the output delay can be adjusted to widen output signals for dead zone mitigation, allowing optimal performance under different operating conditions.
2Duration of action of moving object
If the reset pulse width is increased to mitigate the dead zone, then the output signal width is improved, but the PFD misses signal detection during the reset pulse, reducing the operational range
Solution Approach 1:
The patent separates the reset signal generation and output signal generation into independent processing paths. The reset processing path controls the reset pulse width independently from the output processing path that controls the output signal width. This allows the output signal to be widened for better dead zone mitigation without necessarily increasing the reset pulse width that would cause missed detections.
Solution Approach 2:
The patent changes the timing parameters by introducing independently configurable delays in each processing path. The output delay can be increased to widen the output signal for better dead zone mitigation, while the reset delay can be kept minimal to maintain signal detection reliability, thus resolving the contradiction between these two requirements.
Data Source
AI summary
Described herein is a phase frequency detector (PFD) with a wide operational range. The PFD includes a first flip-flop to receive a reference clock and generate a first output signal based on differences between the reference clock and a feedback clock, a second flip-flop to receive the feedback clock and generate a second output signal based on differences between the reference the feedback clocks, a reset processing path connected to the first flip-flop and second flip-flop, the reset processing path having a reset delay to control a pulse width of a reset signal associated with the first flip-flop and second flip-flop, and an output processing path connected to the first flip-flop and second flip-flop, the output processing path having an output delay to control a pulse width of the first output signal and the second output signal, where the reset processing path and the output processing path are delay independent.