Continuous PFET Cell Layouts for SiGe Local Layout Effects
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Solution Overview
Problem
In standard cell layouts for certain technology nodes, the performance of PFETs is significantly lower than NFETs due to the use of a SiGe channel, which induces a strong local layout effect when the active region is not continuously extended in abutment.
Innovation Solution
The implementation of a continuous active region spanning across PFET regions with specific abutment configurations, including L-shape and U-shape constructs for source-source and source-drain abutments, and the use of filler cells to restrict drain-drain abutments, thereby enhancing PFET performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a SiGe channel is used in PFET, then the transistor can be provided in standard cell layouts, but the PFET performance becomes much lower than NFET due to strong local layout effects when the active region is not continuously extended
Solution Approach 1:
The patent implements a continuous active region that extends across multiple abutting cells without interruption. This continuous extension of the active region in the PFET eliminates the strong local layout effects that occur when the active region is discontinuous, thereby significantly improving PFET performance while maintaining standard cell layout compatibility
Solution Approach 2:
The patent merges multiple separate active regions into a single continuous active region that spans across abutting cells. By combining these regions and removing gaps or interruptions between them, the patent achieves improved PFET performance through continuous carrier transport while maintaining compatibility with standard cell layout methodologies
2Ease of manufacture
If the active region is not continuously extended in abutment, then standard cell layouts can be used, but strong local layout effects are induced that reduce PFET performance
Solution Approach 1:
The patent establishes continuous active regions that extend across abutting cells without interruption. This continuity eliminates the harmful local layout effects by ensuring uninterrupted carrier transport paths, while the overall cell layout structure remains compatible with standard design methodologies
3Reliability
If continuous active regions are implemented with optimized abutment configurations, then PFET performance is significantly improved, but the layout complexity increases with L-shape and U-shape constructs
Solution Approach 1:
The patent applies different abutment configuration patterns (L-shape for drain-source and source-drain interfaces, U-shape for source-source interfaces) to specific local regions where they are most effective. This localized application of optimized configurations improves PFET performance in critical areas while minimizing overall layout complexity
Solution Approach 2:
The patent segments the continuous active region into standardized modular units that can be abutted together in repeating patterns. This segmentation allows the complex continuous active region to be constructed from simpler, reusable building blocks, reducing layout complexity while maintaining the performance benefits of continuity
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.